Technical Note

9/16

www.rohm.com

2011.07 - Rev.B

© 2011 ROHM Co., Ltd. All rights reserved.

BD9673EFJ

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Evaluation Board Layout

Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents

or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies

performance. To help eliminate these problems, the VCC pin should be bypassed to ground with a low ESR ceramic bypass

capacitor with B dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the

VCC pin, and the anode of the catch diode. See Fig.28 for a PCB layout example. The GND pin should be tied directly to

the thermal pad under the IC and the thermal pad.

The thermal pad should be connected to any internal PCB ground planes using multiple VIAs directly under the IC. The LX

pin should be routed to the cathode of the catch diode and to the output inductor. Since the LX connection is the switching

node, the catch diode and output inductor should be located close to the LX pins, and the area of the PCB conductor

minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side ground area must provide

adequate heat dissipating area. The additional external components can be placed approximately as shown. It may be

possible to obtain acceptable performance with alternate PCB layouts; however this layout has been shown to produce

good results and is meant as a guideline.

Fig.28 Evaluation Board Pattern

LX

GND

VC

FB

VCC

BST

EN

SYNC

Output

Inductor

Catch

Diode

Output

Capacitor

Input Bypass

Capacitor

CBST

Topside

Ground

Area

Compensation

Network

Resistor

Divider

VOUT

Route BST Capacitor

Trace on another layer to

provide with wide path for

topside ground

Signal VIA

Thermal VIA

VCC