Technical Note

11/15

www.rohm.com

2011.02 - Rev.A

© 2011 ROHM Co., Ltd. All rights reserved.

BD9328EFJ

FET

L

VIN

●

Layout Pattern Consideration

Two high pulsing current flowing loops exist in the buck regulator system. The first loop, when FET is ON, starts from the

input capacitors, to the VIN terminal, to the SW terminal, to the inductor, to the output capacitors, and then returns to the

input capacitor through GND. The second loop, when FET is OFF, starts from the low FET, to the inductor, to the output

capacitor, and then returns to the low FET through GND. To reduce the noise and improve the efficiency, please minimize

these two loop area. Especially input capacitor, output capacitor and low FET should be connected to GND plain.

PCB Layout may affect the thermal performance, noise and efficiency greatly. So please take extra care when designing

PCB Layout patterns.

・

The thermal Pad on the back side of IC has the great thermal conduction to the chip. So using the GND plain as broad and

wide as possible can help thermal dissipation. And a lot of thermal via for helping the spread of heat to the different layer is

also effective.

・

The input capacitors should be connected as close as possible to the VIN terminal.

・

Keep sensitive signal traces such as trace connected FB and COMP away from SW pin.

・

The inductor and the output capacitors should be placed close to SW pin as much as possible.

COMP

BST

VIN

SW

FB

SS

EN

GND

L

Fig.25 Current loop in Buck regulator system

Fig.26 The example of PCB layout pattern