2

FN8190.4

October 13, 2009

Pin Descriptions

Host Interface Pins

SERIAL OUTPUT (SO)

SO is a push/pull serial data output pin. During a read cycle,

data is shifted out on this pin. Data is clocked out by the

falling edge of the serial clock.

SERIAL INPUT

SI is the serial data input pin. All opcodes, byte addresses

and data to be written to the pots and pot registers are input

on this pin. Data is latched by the rising edge of the serial

clock.

SERIAL CLOCK (SCK)

The SCK input is used to clock data into and out of the

X9401.

CHIP SELECT (CS)

When CS is HIGH, the X9401 is deselected and the SO pin

is at high impedance, and (unless an internal write cycle is

underway) the device will be in the standby state. CS LOW

enables the X9401, placing it in the active power mode. It

should be noted that after a power-up, a HIGH to LOW

transition on CS is required prior to the start of any

operation.

HOLD (HOLD)

HOLD is used in conjunction with the CS pin to select the

device. Once the part is selected and a serial sequence is

underway, HOLD may be used to pause the serial

communication with the controller without resetting the serial

sequence. To pause, HOLD must be brought LOW while

SCK is LOW. To resume communication, HOLD is brought

HIGH, again while SCK is LOW. If the pause feature is not

used, HOLD should be held HIGH at all times.

The address inputs are used to set the least significant 2 bits of the

8-bit slave address. A match in the slave address serial data

stream must be made with the address input in order to

initiate communication with the X9401. A maximum of 4

devices may occupy the SPI serial bus.

Potentiometer Pins

connections on either end of a mechanical potentiometer.

VW (VW0 - VW3)/ RW (RW0 - RW3)

The wiper outputs are equivalent to the wiper output of a

mechanical potentiometer.

HARDWARE WRITE PROTECT INPUT (WP)

The WP pin when LOW prevents nonvolatile writes to the

Wiper Counter Registers.

Ordering Information

PART

NUMBER

PART

MARKING

LIMITS

(V)

POTENTIOMETER

ORGANIZATION

(k

Ω)

TEMP

RANGE

(°C)

PACKAGE

PKG.

DWG. #

X9401WS24IZ* (Note 1)

X9401WS ZI

5 ±10%

10

-40 to +85

24 Ld SOIC (300 mil) (Pb-free)

M24.3

X9401WS24I

X9401WS I

-40 to +85

24 Ld SOIC (300 mil)

M24.3

X9401WS24Z* (Note 1)

X9401WS Z

-40 to +85

24 Ld SOIC (300 mil)

M24.3

X9401WV24IZ* (Note 1)

X9401WV ZI

-40 to +85

24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

X9401WV24Z* (Note 1)

X9401WV Z

-40 to +85

24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

X9401WS24I-2.7* (Note 2) X9401WS G

2.7 to 5.5

-40 to +85

24 Ld SOIC (300 mil)

M24.3

X9401WS24IZ-2.7* (Note)

X9401WS ZG

-40 to +85

24 Ld SOIC (300 mil) (Pb-free)

M24.3

X9401WS24Z-2.7* (Note 1) X9401WS ZF

-40 to +85

24 Ld SOIC (300 mil) (Pb-free)

M24.3

X9401WV24-2.7

X9401WV F

-40 to +85

24 Ld TSSOP (4.4mm)

MDP0044

X9401WV24IZ-2.7* (Note 1) X9401WV ZG

-40 to +85

24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

X9401WV24Z-2.7* (Note 1) X9401WV ZF

-40 to +85

24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

*Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTES:

1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%

matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC

J STD-020.

2. Not recommended for new designs.

X9401