Technical Note

9/10

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2011.05 - Rev.B

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BA6219BFP-Y,BA6222

11)

Testing on application boards

When testing the IC on an application board, connecting a capacitor to a low impedance pin subjects the IC to stress.

Therefore, always discharge capacitors after each process or step. Always turn the IC's power supply off before

connecting it to or removing it from the test setup during the inspection process. Ground the IC during assembly steps

as an antistatic measure. Use similar precaution when transporting or storing the IC.

12) Regarding the input pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements, in order to keep them

isolated. P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example, the relation between each potential is as follows:

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, as well as operating malfunctions and physical damage. Therefore, do not use methods by

which parasitic diodes operate, such as applying a voltage lower than the GND (P substrate) voltage to an input pin.

Parasitic

element

Appendix: Example of monolithic IC structure

Resistor

Transistor (NPN)

N

N

N

P

+

P

+

P

P substrate

GND

Parasitic element

Pin A

N

N

P

+

P

+

P

P substrate

GND

Parasitic element

Pin B

C

B

E

N

GND

Pin A

Pin B

Other adjacent elements

E

B

C

GND

Parasitic

element