5

FN8109.2

August 28, 2009

The Toggle Bit can eliminate the chore of saving and

fetching the last address and data in order to implement

DATA Polling. This can be especially helpful in an array

comprised of multiple X28HC64 memories that is frequently

updated. Toggle Bit Polling can also provide a method for

status checking in multiprocessor applications. The timing

diagram in Figure 4 illustrates the sequence of events on the

bus. The software flow diagram in Figure 5 illustrates a

method for polling the Toggle Bit.

Hardware Data Protection

The X28HC64 provides two hardware features that protect

nonvolatile data from inadvertent writes.

• Write Inhibit—Holding either OE LOW, WE HIGH, or CE

HIGH will prevent an inadvertent write cycle during power-

up and power-down, maintaining data integrity.

Software Data Protection

The X28HC64 offers a software controlled data protection

feature. The X28HC64 is shipped from Intersil with the software

data protection NOT ENABLED; that is, the device will be in the

standard operating mode. In this mode data should be

protected during power-up/-down operations through the use of

external circuits. The host would then have open read and write

The X28HC64 can be automatically protected during power-

up and power-down without the need for external circuits by

employing the software data protection feature. The internal

software data protection circuit is enabled after the first write

operation utilizing the software algorithm. This circuit is

nonvolatile and will remain set for the life of the device,

unless the reset command is issued.

Once the software protection is enabled, the X28HC64 is

also protected from inadvertent and accidental writes in the

powered-up state. That is, the software algorithm must be

issued prior to writing additional data to the device.

Software Algorithm

Selecting the software data protection mode requires the

host system to precede data write operations by a series of

three write operations to three specific addresses. Refer to

Figure 6 and 7 for the sequence. The three-byte sequence

opens the page write window, enabling the host to write from

one to sixty-four bytes of data. Once the page load cycle has

been completed, the device will automatically be returned to

the data protected state.

CE

OE

WE

X28HC64

LAST

WRITE

HIGH Z

*

*

READY

FIGURE 4. TOGGLE BIT BUS SEQUENCE

COMPARE

NO

YES

OK?

COMPARE

ACCUM WITH

ADDR N

LOAD ACCUM

FROM ADDR N

LAST WRITE

READY

YES

FIGURE 5. TOGGLE BIT SOFTWARE FLOW

X28HC64