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KAD5610P-17Q72 Datasheet(PDF) 9 Page - Intersil Corporation |
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KAD5610P-17Q72 Datasheet(HTML) 9 Page - Intersil Corporation |
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9 / 30 page  9 FN6810.2 September 10, 2009 46 RLVDS LVDS Bias Resistor (connect to OVSS with a 10k Ω, 1% resistor) 47 CLKOUTN [NC] LVDS Clock Output Complement [NC in LVCMOS] 48 CLKOUTP [CLKOUT] LVDS Clock Output True [ LVCMOS CLKOUT] 49 D4N [NC] LVDS Bit 4 Output Complement [NC in LVCMOS] 50 D4P [D4] LVDS Bit 4 Output True [LVCMOS Bit 4] 51 D5N [NC] LVDS Bit 5 Output Complement [NC in LVCMOS] 52 D5P [D5] LVDS Bit 5 Output True [LVCMOS Bit 5] 53 D6N [NC] LVDS Bit 6 Output Complement [NC in LVCMOS] 54 D6P [D6] LVDS Bit 6 Output True [LVCMOS Bit 6] 57 D7N [NC] LVDS Bit 7 Output Complement [NC in LVCMOS] 58 D7P [D7] LVDS Bit 7 Output True [LVCMOS Bit 7] 59 D8N [NC] LVDS Bit 8 Output Complement [NC in LVCMOS] 60 D8P [D8] LVDS Bit 8 Output True [LVCMOS Bit 8] 61 D9N [NC] LVDS Bit 9 (MSB) Output Complement [NC in LVCMOS] 62 D9P [D9] LVDS Bit 9 (MSB) Output True [LVCMOS Bit 9] 63 ORN [NC] LVDS Over Range Complement, [NC in LVCMOS] 64 ORP [OR] LVDS Over Range True [LVCMOS Over Range] 66 SDO SPI Serial Data Output (4.7k Ω pull-up to OVDD is required) 67 CSB SPI Chip Select (active low) 68 SCLK SPI Clock 69 SDIO SPI Serial Data Input/Output 70 OUTFMT Output Data Format (Two’s Comp., Gray Code, Offset Binary) Exposed Paddle AVSS Analog Ground NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection). Pin Descriptions (Continued) PIN # LVDS [LVCMOS] NAME LVDS [LVCMOS] FUNCTION KAD5610P |
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