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ISLA112P50 Datasheet(PDF) 9 Page - Intersil Corporation |
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ISLA112P50 Datasheet(HTML) 9 Page - Intersil Corporation |
9 / 34 page ISLA112P50 9 FN7604.2 August 1, 2011 Switching Specifications PARAMETER CONDITION SYMBOL MIN TYP MAX UNITS A/D OUTPUT Aperture Delay tA 375 ps RMS Aperture Jitter jA 90 fs Input Clock to Output Clock Propagation Delay AVDD, OVDD = 1.8V, TA = +25°C tCPD 2.6 2.9 3.3 ns AVDD, OVDD = 1.7V to 1.9V, TA = -40°C to +85°C tCPD 2.0 2.6 3.6 ns Relative Input Clock to Output Clock Propagation Delay Matching (Note 16) AVDD, OVDD = 1.7V to 1.9V, TA = -40°C to +85°C dtCPD -450 450 ps Input Clock to Data Propagation Delay, LVDS Mode tPD 1.74 2.6 3.83 ns Output Clock to Data Propagation Delay LVDS or CMOS Mode tDC -250 0 250 ps Synchronous Clock Divider Reset Setup Time (with respect to the positive edge of CLKP) tRSTS 300 75 ps Synchronous Clock Divider Reset Hold Time (with respect to the positive edge of CLKP) tRSTH 450 150 ps Synchronous Clock Divider Reset Recovery Time DLL recovery time after Synchronous Reset tRSTRT 52 µs Latency (Pipeline Delay) (Note 17) L 17 cycles Overvoltage Recovery tOVR 1cycles SPI INTERFACE (Notes 18, 19) SCLK Period Write Operation t CLK 32 cycles (Note 18) Read Operation tCLK 132 cycles CSB ↓ to SCLK↑ Setup Time Read or Write tS 2cycles CSB ↑ after SCLK↑ Hold Time Read or Write tH 11 cycles Data Valid to SCLK ↑ Setup Time Write tDSW 2cycles Data Valid after SCLK ↑ Hold Time Write tDHW 8cycles Data Valid after SCLK ↓ Time Read tDVR 33 cycles Data Invalid after SCLK ↑ Time Read tDHR 6cycles Sleep Mode CSB ↓ to SCLK↑ Setup Time (Note 20) Read or Write in Sleep Mode tS 150 µs NOTES: 14. The Tri-Level Inputs internal switching thresholds are approximately 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending on desired function. 15. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing. 16. The relative propagation delay is the timing of the output clock of any A/D with respect to the nominal timing of any other A/D, given that all devices are clocked at the same time and are matched in temperature and voltage. It is specified over the full operating temperature and voltage range, and is established by characterization and not production tested. 17. The pipeline latency of this converter is fixed. 18. SPI Interface timing is directly proportional to the A/D sample period (tSAMPLE). 19. The SPI may operate asynchronously with respect to the A/D sample clock. 20. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal mode CSB setup time (4ns min). |
Similar Part No. - ISLA112P50_11 |
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Similar Description - ISLA112P50_11 |
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