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5962R0922501QXC Datasheet(PDF) 4 Page - Intersil Corporation |
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5962R0922501QXC Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 16 page ISL70001SRH 4 FN6947.1 May 23, 2011 12 SS This pin is the soft-start input. Connect a ceramic capacitor from this pin to DGND to set the soft-start output ramp time in accordance with Equation 1: Where: tSS = Soft-start output ramp time CSS = Soft-start capacitor VREF = Reference voltage (0.6V typical) ISS = Soft-start charging current (23µA typical) Soft-start time is adjustable from approximately 2ms to 200ms. The range of the soft-start capacitor should be 82nF to 8.2µF, inclusive. 13, 14 DVDD These pins are the bias supply inputs to the internal digital control circuitry. Connect these pins together at the IC and locally filter them to DGND using a 1 Ω resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC. 15, 16 DGND These pins are the digital ground associated with the internal digital control circuitry. Connect these pins directly to the ground plane. 17, 18 AGND These pins are the analog ground associated with the internal analog control circuitry. Connect these pins directly to the ground plane. 19 AVDD This pin is the bias supply input to the internal analog control circuitry. Locally filter this pin to AGND using a 1 Ω resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC. 20 REF This pin is the internal reference voltage output. Bypass this pin to AGND with a 220nF ceramic capacitor located as close as possible to the IC. The bypass capacitor is needed to mitigate SEE. No current (sourcing or sinking) is available from this pin. 21 FB This pin is the voltage feedback input to the internal error amplifier. Connect a resistor from FB to VOUT and from FB to AGND to adjust the output voltage in accordance with Equation 2: Where: VOUT = Output voltage VREF = Reference voltage (0.6V typical) RT = Top divider resistor (Must be 1kΩ) RB = Bottom divider resistor The top divider resistor must be 1k Ω to mitigate SEE. Connect a 4.7nF ceramic capacitor across RT to mitigate SEE and to improve stability margins. 22 EN This pin is the enable input to the IC. This is a comparator type input with a rising threshold of 0.6V and programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to AGND with a 10nF ceramic capacitor to mitigate SEE. 23 PORSEL This pin is the input for selecting the rising and falling POR (Power-On-Reset) thresholds. For a nominal 5V supply, connect this pin to DVDD. For a nominal 3.3V supply, connect this pin to DGND. For nominal supply voltages between 5V and 3.3V, connect this pin to DGND. Pin Descriptions (Continued) PIN NUMBER PIN NAME DESCRIPTION tSS CSS VREF ⋅ ISS ⁄ = (EQ. 1) VOUT VREF 1RT RB ⁄ () + [] ⋅ = (EQ. 2) |
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