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MAX11102ATB+ Datasheet(PDF) 12 Page - Maxim Integrated Products |
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MAX11102ATB+ Datasheet(HTML) 12 Page - Maxim Integrated Products |
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12 / 30 page  12 _____________________________________________________________________________________ 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11111) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps, CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (SCLK, CS) Digital Input High Voltage VIH 0.75 x VOVDD V Digital Input Low Voltage VIL 0.25 x VOVDD V Digital Input Hysteresis VHYST 0.15 x VOVDD V Digital Input Leakage Current IIL Inputs at GND or VDD 0.001 Q 1 F A Digital Input Capacitance CIN 2 pF DIGITAL OUTPUT (DOUT) Output High Voltage VOH ISOURCE = 200µA (Note 2) 0.85 x VOVDD V Output Low Voltage VOL ISINK = 200µA (Note 2) 0.15 x VOVDD V High-Impedance Leakage Current IOL Q 1.0 F A High-Impedance Output Capacitance COUT 4 pF POWER SUPPLY Positive Supply Voltage VDD 2.2 3.6 V Digital I/O Supply Voltage VOVDD 1.5 VDD V Positive Supply Current (Full-Power Mode) IVDD VAIN_ = VGND 3.3 mA IOVDD VAIN_ = VGND 0.33 Positive Supply Current (Full-Power Mode), No Clock IVDD 1.98 mA Power-Down Current IPD Leakage only 1.3 10 F A Line Rejection VDD = +2.2V to +3.6V, VREF = 2.2V 0.17 LSB/V TIMING CHARACTERISTICS (Note 1) Quiet Time tQ (Note 2) 4 ns CS Pulse Width t1 (Note 2) 10 ns CS Fall to SCLK Setup t2 (Note 2) 5 ns CS Falling Until DOUT High- Impedance Disabled t3 (Note 2) 1 ns Data Access Time After SCLK Falling Edge (Figure 2) t4 VOVDD = 2.2V - 3.6V 15 ns VOVDD = 1.5V - 2.2V 16.5 SCLK Pulse Width Low t5 Percentage of clock period (Note 2) 40 60 % SCLK Pulse Width High t6 Percentage of clock period (Note 2) 40 60 % Data Hold Time From SCLK Falling Edge t7 Figure 3 5 ns SCLK Falling Until DOUT High- Impedance t8 Figure 4 (Note 2) 2.5 14 ns Power-Up Time Conversion cycle (Note 2) 1 Cycle |
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