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DS3911 Datasheet(PDF) 9 Page - Maxim Integrated Products |
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DS3911 Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 24 page ����������������������������������������������������������������� Maxim Integrated Products 9 DS3911 Temperature-Controlled, Nonvolatile, I2C Quad DAC DAC Power-On Values Each 10-bit DAC is controlled directly by the value in its corresponding DAC VALUE register. Each DAC also has a DAC POR register that contains the power-on-reset (POR) value for the associated DAC, along with two con- trol bits: enable (EN) and polarity (POL). See the Lower Memory Register Descriptions section for complete lower memory descriptions. The DAC POR (DAC0 POR, DAC1 POR, DAC2 POR, and DAC3 POR) registers are shadowed EEPROM with func- tionality controlled by the shadow EEPROM bit (SEE). If the SEE bit is high, the DAC POR registers function as SRAM only. If the SEE bit is low, the registers are shad- owed EEPROM and EEPROM write timing, tW, must be observed. On power-up, the initial DAC settings are always trans- ferred from the DAC POR registers to the corresponding DAC VALUE registers. Manual Control Mode On power-up, the device starts performing temperature conversions and the DAC VALUE register whose corre- sponding EN bit is set is updated by the LUT controller as described in the Lookup Table Mode section. Clearing the EN bit enables I2C writes to the corresponding DAC VALUE and disables LUT controller updates. This allows the indi- vidual DACs whose EN bit is cleared to be controlled by writing the corresponding DAC VALUE register directly. Lookup Table Mode The device has four nonvolatile memory tables, one for each of the four DACs. Each memory table is associated with an individual DAC as follows: Table 04h (DAC0), Table 05h (DAC1), Table 06h (DAC2), Table 07h (DAC3), and selected by setting the table select bits, TS[3:0], in the CTRL regis- ter. Each DAC memory table consists of a DAC LUT table (addresses 80h–AFh) (DAC0 LUT, DAC1 LUT, DAC2 LUT, and DAC3 LUT) and a DAC OFFSET table (addresses F8h–FFh) (DAC0 OFFSET, DAC1 OFFSET, DAC2 OFFSET, and DAC3 OFFSET). Because these four memory tables all share the same address and register mapping, the TS[3:0] bits must be used to select among them. Each LUT address represents as little as a 2N change in temperature. Table 1 shows the full temperature-to- register mapping. The first DAC OFFSET address corresponds to 32N of temperature. After this, every 16N of temperature con- verts into one DAC OFFSET address slot. Table 2 shows the full temperature-to-register mapping. The TINDEX register points to a LUT address slot. The TINDEX register can operate in two modes, as defined by the AEN bit. When the AEN bit is cleared, I2C writes to the TINDEX register are enabled, and updates from the LUT controller are blocked. The register can be used to force DAC updates to be based on the user-selected index. The TINDEX register directly addresses the LUT Table1.LUTTemperatureMapping Table2.OffsetTemperatureMapping ROW (HEX) BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 4NCLUT 80h < -36N -36N -32N -28N -24N -20N -16N -12N 88h -8N -4N 0N +4N +8N +12N +16N +20N 90h +24N +28N +32N +36N +40N +44N +48N +52N 2NCLUT 98h +56N +58N +60N +62N +64N +66N +68N +70N A0h +72N +74N +76N +78N +80N +82N +84N +86N A8h +88N +90N +92N +94N +96N +98N +100N R +102N ROW (HEX) BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 F8h < -8N -8N +8N +24N +40N +56N +72N R +88N |
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