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TPS61175 Datasheet(PDF) 9 Page - Texas Instruments |
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TPS61175 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 24 page 0 500 1000 1500 2000 2500 3000 3500 10 100 1000 ExternalResistor-kW TPS61175 www.ti.com SLVS892A – DECEMBER 2008 – REVISED OCTOBER 2010 Figure 13. Switching Frequency vs External Resistor Alternatively, the TPS61175 switching frequency will synchronize to an external clock signal that is applied to the SYNC pin. The logic level of the external clock is shown in the specification table. The duty cycle of the clock is recommended in the range of 10% to 90%. The resistor also must be connected to the FREQ pin when IC is switching by the external clock. The external clock frequency must be within ±20% of the corresponding frequency set by the resistor. For example, if the corresponding frequency as set by a resistor on the FREQ pin is 1.2-MHz, the external clock signal should be in the range of 0.96-MHz to 1.44-MHz. If the external clock signal is higher than the frequency per the resistor on the FREQ pin, the maximum duty cycle specification (DMAX) should be lowered by 2%. For instance, if the resistor set value is 2.5MHz, and the external clock is 3MHz, DMAX is 87% instead of 89%. SOFT START The TPS61175 has a built-in soft start circuit which significantly reduces the start-up current spike and output voltage overshoot. When the IC is enabled, an internal bias current (6-mA typically) charges a capacitor (C3) on the SS pin. The voltage at the capacitor clamps the output of the internal error amplifier that determines the duty cycle of PWM control, thereby the input inrush current is eliminated. Once the capacitor reaches 1.8-V, the soft start cycle is completed and the soft start voltage no longer clamps the error amplifier output. Refer to Figure 13 for the soft start waveform. See Table 2 for C3 and corresponding soft start time. A 47-nF capacitor eliminates the output overshoot and reduces the peak inductor current for most applications. Table 2. Soft Start Time vs C3 Vin (V) Vout (V) Load (A) Cout (mF) fSW (MHz) C3 (nF) tSS(ms) Overshot (mV) 47 4 none 5 24 0.4 10 1.2 10 0.8 210 100 6.5 none 12 35 0.6 10 2 10 0.4 300 When the EN is pulled low for 10-ms, the IC enters shutdown and the SS capacitor discharges through a 5k Ω resistor for the next soft start. OVERCURRENT PROTECTION The TPS61175 has a cycle-by-cycle overcurrent limit protection that turns off the power switch once the inductor current reaches the overcurrent limit threshold. The PWM circuitry resets itself at the beginning of the next switch cycle. During an overcurrent event, the output voltage begins to droop as a function of the load on the output. When the FB voltage drops lower than 0.9-V, the switching frequency is automatically reduced to 1/4 of the set value. The switching frequency does not reset until the overcurrent condition is removed. This feature is disabled during soft start. Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): TPS61175 |
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