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TMS320R2812ZHHA Datasheet(PDF) 8 Page - Texas Instruments |
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TMS320R2812ZHHA Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 154 page  Figures 9 June 2004 − Revised June 2006 SPRS257C Figure 6−15. TDIRx Timing 103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−16. EVASOC Timing 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−17. EVBSOC Timing 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−18. External Interrupt Timing 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−19. General-Purpose Output Timing 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−20. GPIO Input Qualifier − Example Diagram for QUALPRD = 1 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−21. General-Purpose Input Timing 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−22. SPI Master Mode External Timing (Clock Phase = 0) 109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−23. SPI Master External Timing (Clock Phase = 1) 111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−24. SPI Slave Mode External Timing (Clock Phase = 0) 113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−25. SPI Slave Mode External Timing (Clock Phase = 1) 114 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−26. Relationship Between XTIMCLK and SYSCLKOUT 117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−27. Example Read Access 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−28. Example Write Access 120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−29. Example Read With Synchronous XREADY Access 122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−30. Example Read With Asynchronous XREADY Access 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−31. Write With Synchronous XREADY Access 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−32. Write With Asynchronous XREADY Access 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−33. External Interface Hold Waveform 128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−34. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) 129 . . . . . . . . . . . . . . . . . . . . . Figure 6−35. ADC Analog Input Impedance Model 133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−36. ADC Power-Up Control Bit Timing 133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−37. Sequential Sampling Mode (Single-Channel) Timing 135 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−38. Simultaneous Sampling Mode Timing 136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−39. McBSP Receive Timing 140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−40. McBSP Transmit Timing 140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6−41. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 141 . . . . . . . . . . . . . . . . . . . . . . Figure 6−42. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 142 . . . . . . . . . . . . . . . . . . . . . . Figure 6−43. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 143 . . . . . . . . . . . . . . . . . . . . . . Figure 6−44. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 144 . . . . . . . . . . . . . . . . . . . . . . |
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