13 BOOT

12 PH

11 PH

10 EN

9 SS/TR

GND 2

GND 3

PVIN 4

PVIN 5

VIN 6

7

8

1

14

RT/CLK

PWRGD

VSENSE

COMP

(15)

Exposed

Thermal Pad

TPS54320

www.ti.com

SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010

DEVICE INFORMATION

PIN ASSIGNMENTS

PIN FUNCTIONS

PIN

DESCRIPTION

NAME

No.

RT/CLK

1

Automatically selects between RT mode and CLK mode. An external timing resistor adjusts the switching

frequency of the device; In CLK mode, the device synchronizes to an external clock.

GND

2, 3

Return for control circuitry and low-side power MOSFET.

PVIN

4, 5

Power input. Supplies the power switches of the power converter.

VIN

6

Supplies the control circuitry of the power converter.

VSENSE

7

Inverting input of the gm error amplifier.

COMP

8

Error amplifier output, and input to the output switch current comparator. Connect frequency compensation to this

pin.

SS/TR

9

Slow-start and tracking. An external capacitor connected to this pin sets the internal voltage reference rise time.

The voltage on this pin overrides the internal reference. It can be used for tracking and sequencing.

EN

10

Enable pin. Float to enable. Adjust the input undervoltage lockout with two resistors.

PH

11, 12

The switch node.

BOOT

13

A bootstrap cap is required between BOOT and PH. The voltage on this cap carries the gate drive voltage for the

high-side MOSFET.

PWRGD

14

Open drain Power Good fault pin. Asserts low due to thermal shutdown, under-voltage, over-voltage, EN

shutdown, or during slow start.

Exposed

15

Thermal pad of the package and signal ground. It must be soldered down for proper operation.

Thermal

PAD

Copyright © 2010, Texas Instruments Incorporated

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