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TMS320F240PQS Datasheet(PDF) 10 Page - Texas Instruments |
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TMS320F240PQS Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 105 page  TMS320F240 DSP CONTROLLER SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Terminal Functions (Continued) TERMINAL TYPE† DESCRIPTION NAME NO. TYPE† DESCRIPTION TEST SIGNALS (CONTINUED) TRST 32 I JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its function- al mode, and the test reset signals are ignored. EMU0 38 I/O/Z Emulator pin 0. When TRST is driven low, EMU0 must be high for activation of the /OFF condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output through the scan. EMU1/OFF 39 I/O/Z Emulator pin 1/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as input/output through JTAG scan. When TRST is driven low, this pin is configured as OFF. When EMU1/OFF is active low, it puts all output drivers in the high-impedance state. OFF is used exclusively for testing and emulation purposes (not for multiprocessing applications); therefore, for OFF condition, the following conditions apply: TRST = low, EMU0 = high, EMU1/OFF = low RESERVED 42 I Reserved for test. This pin has an internal pulldown and must be left unconnected. † I = input, O = output, Z = high impedance |
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