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MSP430F415IRTDR Datasheet(PDF) 11 Page - Texas Instruments |
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MSP430F415IRTDR Datasheet(HTML) 11 Page - Texas Instruments |
11 / 64 page MSP430x41x MIXED SIGNAL MICROCONTROLLER SLAS340J − MAY 2001 − REVISED DECEMBER 2008 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up External reset Watchdog Flash memory WDTIFG KEYV (see Note 1) Reset 0FFFEh 15, highest NMI Oscillator fault Flash memory access violation NMIIFG (see Notes 1 and 3) OFIFG (see Notes 1 and 3) ACCVIFG (see Notes 1 and 3) (Non)maskable (Non)maskable (Non)maskable 0FFFCh 14 Timer1_A5 (see Note 4) TA1CCR0 CCIFG (see Note 2) Maskable 0FFFAh 13 Timer1_A5 (see Note 4) TA1CCR1 to TA1CCR4 CCIFGs and TA1CTL TAIFG (see Notes 1 and 2) Maskable 0FFF8h 12 Comparator_A CMPAIFG Maskable 0FFF6h 11 Watchdog timer WDTIFG Maskable 0FFF4h 10 0FFF2h 9 0FFF0h 8 0FFEEh 7 Timer_A3/Timer0_A3 TACCR0/TA0CCR0 CCIFG (see Note 2) Maskable 0FFECh 6 Timer_A3/Timer0_A3 TACCR1/TA0CCR1, TACCR2/TA0CCR2 CCIFGs and TACLT/TA0CTL TAIFG (see Notes 1 and 2) Maskable 0FFEAh 5 I/O port P1 (eight flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0FFE8h 4 0FFE6h 3 0FFE4h 2 I/O port P2 (eight flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0FFE2h 1 Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest NOTES: 1. Multiple source flags 2. Interrupt flags are located in the module. 3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot. 4. Implemented in MSP430x415 and MSP430x417 devices only |
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