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MSP430F5508IZQE Datasheet(PDF) 2 Page - Texas Instruments |
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MSP430F5508IZQE Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 110 page  MSP430F550x, MSP430F5510 SLAS645F – JULY 2009 – REVISED MARCH 2011 www.ti.com DESCRIPTION The Texas Instruments MSP430 ™ family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with extensive low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 5 µs. The MSP430F5510, MSP430F5509, and MSP430F5508 devices are microcontroller configurations with integrated USB and PHY supporting USB 2.0, four 16-bit timers, a high-performance 10-bit analog-to-digital converter (ADC), two universal serial communication interfaces (USCI), hardware multiplier, DMA, real-time clock module with alarm capabilities, and 31 or 47 I/O pins. The MSP430F5507, MSP430F5506, MSP430F5505, and MSP430F5504 devices are microcontroller configurations with integrated USB and PHY supporting USB 2.0, four 16-bit timers, a high-performance 10-bit analog-to-digital converter (ADC), two universal serial communication interfaces (USCI), hardware multiplier, DMA, real-time clock module with alarm capabilities, and 31 I/O pins. The MSP430F5503, MSP430F5502, and MSP430F5500 include all of these peripherals but have a comparator instead of the 10-bit ADC. Typical applications include analog and digital sensor systems, data loggers, etc., that require connectivity to various USB hosts. Family members available are summarized in Table 1. Table 1. Family Members USCI PROGRAM SRAM ADC10_A Comp_B PACKAGE CHANNEL A: CHANNEL B: DEVICE MEMORY Timer_A(2) Timer_B(3) I/O (KB)(1) (CH) (CH) TYPE UART/LIN/ SPI/I2C (KB) IrDA/SPI 64 RGC, 10 ext / 2 int 8 47 80 ZQE MSP430F5510 32 4 + 2 5, 3, 3 7 2 2 48 PT, 6 ext / 2 int 4 31 48 RGZ 64 RGC, 10 ext / 2 int 8 47 80 ZQE MSP430F5509 24 4 + 2 5, 3, 3 7 2 2 48 PT, 6 ext / 2 int 4 31 48 RGZ, 64 RGC, 10 ext / 2 int 8 47 80 ZQE MSP430F5508 16 4 + 2 5, 3, 3 7 2 2 48 PT, 6 ext / 2 int 4 31 48 RGZ, MSP430F5507 32 4 + 2 5, 3, 3 7 1 1 6 ext / 2 int - 31 48 RGZ MSP430F5506 24 4 + 2 5, 3, 3 7 1 1 6 ext / 2 int - 31 48 RGZ MSP430F5505 16 4 + 2 5, 3, 3 7 1 1 6 ext / 2 int - 31 48 RGZ 48 PT, MSP430F5504 8 4 + 2 5, 3, 3 7 1 1 6 ext / 2 int - 31 48 RGZ MSP430F5503 32 4 + 2 5, 3, 3 7 1 1 - 4 31 48 RGZ MSP430F5502 24 4 + 2 5, 3, 3 7 1 1 - 4 31 48 RGZ MSP430F5501 16 4 + 2 5, 3, 3 7 1 1 - 4 31 48 RGZ MSP430F5500 8 4 + 2 5, 3, 3 7 1 1 - 4 31 48 RGZ (1) The additional 2-KB USB SRAM that is listed can be used as general purpose SRAM when USB is not in use. (2) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively. (3) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively. 2 Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated |
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