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TRF7970A Datasheet(PDF) 2 Page - Texas Instruments |
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TRF7970A Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 83 page  MUX RX_IN1 RX_IN2 PHASE & AMPLITUDE DETECTOR GAIN RSSI (AUX) LOGIC STATE CONTROL LOGIC [CONTROL REGISTERS & COMMAND LOGIC] 128 BYTE FIFO MCU INTERFACE VDD_I/O I/O_0 I/O_1 I/O_2 I/O_3 I/O_4 I/O_5 I/O_6 I/O_7 IRQ SYS_CLK DATA _CLK ISO PROTOCOL HANDLING DECODER RSSI (EXTERNAL) PHASE & AMPLITUDE DETECTOR GAIN RSSI (MAIN) FILTER & AGC DIGITIZER BIT FRAMING FRAMING SERIAL CONVERSION CRC & PARITY TRANSMITTER ANALOG FRONT END TX_OUT VDD_PA VSS_PA DIGITAL CONTROL STATE MACHINE CRYSTAL / OSCILLATOR TIMING SYSTEM EN EN2 ASK/OOK MOD OSC_IN OSC_OUT VOLTAGE SUPPLY REGULATOR SYSTEMS [SUPPLY REGULATORS , REFERENCE VOLTAGES ] VSS_A VSS_RF VDD_RF VDD_X VSS_D VSS VIN VDD_A BAND_GAP RF Level Detector TRF7970A SLOS743 – AUGUST 2011 www.ti.com The TRF7970A is configured by selecting the desired protocol in the control registers. Direct access to all control registers allows fine tuning of various reader parameters as needed. Documentation, reference designs, EVM, and TI MCU (MSP430, ARM) source code are available. Figure 1-1. Block Diagram 1.3.1 Detailed Description RFID/NFC Operation – Reader/Writer The TRF7970A is a high performance 13.56-MHz HF RFID/NFC Transceiver IC comprised of an integrated analog front end (AFE) and a built-in data framing engine for ISO15693, ISO14443A, ISO14443B, and FeliCa. This includes data rates up to 848 kbps for ISO14443 with all framing and synchronization tasks on board (in default mode). The TRF7970A also supports NFC Tag Type 1, 2, 3, and 4 operations. This architecture enables the customer to build a complete cost-effective yet high-performance multi-protocol 13.56-MHz RFID/NFC system together with a low-cost microcontroller (for example, MSP430). Other standards and even custom protocols can be implemented by using two of the Direct Modes that the device offers. These Direct Modes (0 and 1) allow the user to fully control the analog front end (AFE) and also gain access to the raw subcarrier data or the unframed but already ISO formatted data and the associated (extracted) clock signal. The receiver system has a dual input receiver architecture. The receivers also include various automatic and manual gain control options. The received input bandwidth can be selected to cover a broad range of input subcarrier signal options. 2 Introduction Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TRF7970A |
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