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PCF8574 Datasheet(PDF) 8 Page - NXP Semiconductors |
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PCF8574 Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 24 page  2002 Nov 22 8 Philips Semiconductors Product specification Remote 8-bit I/O expander for I2C-bus PCF8574 6.4 Acknowledge The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit (see Fig.8). The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. Fig.8 Acknowledgment on the I2C-bus. handbook, full pagewidth MBC602 S START condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER |
Similar Part No. - PCF8574 |
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Similar Description - PCF8574 |
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