PCA24S08A_1

© NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 01 — 19 January 2010

6 of 24

NXP Semiconductors

PCA24S08A

1024

× 8-bit CMOS EEPROM with access protection

The general command encoding used by the serial port for EEPROM accesses is shown

in Figure 11, where B[2:0] is the block number, P[2:0] is the page number within the block

and A[3:0] is the byte address within the page. Bits denoted as ‘X’ are ignored by the

device.

6.2.2 Page write

The PCA24S08A is capable of a 16-byte page write operation. It is initiated in the same

manner as the byte write operation. The master can transit 16 data bytes within one

transmission. After receipt of each byte, the PCA24S08A will respond with an

acknowledge. The typical E/W time in this mode is 5 ms.

After the receipt of each data byte, the four low-order bits of the word address are

internally incremented. The six high-order bits of the address remain unchanged. The

After a write to the last byte in a page, the internal address is wrapped around to point to

the beginning of that page. If the master transmits more than 16 bytes prior to generating

and the whole transmission will be ignored and no programming will be done. As in the

byte write operation, all inputs are disabled until completion of the internal write cycles.

transmission.

During the E/W cycle the slave receiver does not acknowledge if addressed via the

Fig 6.

Auto-increment memory word address (2 byte write)

002aae791

0

1

0

1

B2 B1

0

A

S

1

A

P

START condition

R/W acknowledge

from slave

acknowledge

from slave

word address

STOP condition

A

acknowledge

from slave

word

address

P2 P1 P0 A3 A2 A1 A0

B0

DATA

A

acknowledge

from slave

DATA

auto-increment

word address

auto-increment

word address