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E647ATF Datasheet(PDF) 5 Page - Semtech Corporation |
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E647ATF Datasheet(HTML) 5 Page - Semtech Corporation |
5 / 13 page 5 2000 Semtech Corp. www.semtech.com EDGE HIGH-PERFORMANCE PRODUCTS Edge647 Load The Edge647 provides a total of 3 analog switches. Individual switches vary in both their on resistance and their on/off time (see Table 4). Like the driver digital inputs, the switch matrix control inputs SW0-3 EN* are technology independent as VBB determines their threshold level. The switch control is documented in Table 3. Table 3. Switch Matrix Truth Table Table 4. Switch Matrix Characteristics Do NOT leave any digital input pins floating. Circuit Description (continued) Receiver Functionality The Edge647 supports an on-board window comparator. CVB and CVA are high impedance analog inputs which establish the threshold voltages. COMPA and COMPB are the digital outputs which reflect the real time status of VINP. Table 2 summarizes the relationship between the threshold levels, VINP, and the output signals. Table 2. Comparator Truth Table Comparator Outputs The comparator outputs are 50 Ω output impedance non- tristatable drivers designed to cleanly drive 50 Ω transmission lines without requiring any external series termination resistors. Input pins LOW LEVEL and HIGH LEVEL establish the logic 0 and 1 levels respectively. In normal operation, LOW LEVEL would be connected to ground and HIGH LEVEL would be connected to a system VDD supply, producing CMOS digital swings at the output. However, the comparator outputs are technology independent in that they can drive PECL, 3V CMOS, ECL, LV CMOS, GTL, and custom levels by varying LOW LEVEL and HIGH LEVEL. For example, should a 3V swing be desired, HIGH LEVEL could be connected to a 3.0V power supply. Notice that HIGH LEVEL and LOW LEVEL provide both the voltage level and the current for the comparator outputs. HIGH LEVEL and LOW LEVEL may be varied between +5V and -2V. P N I VA P M O CB P M O C A V C < P N I V A V C > P N I V 1 0 X X B V C < P N I V B V C > P N I V X X 0 1 s t u p n I l o r t n o Cs u t a t S 1 = * N E 0 W S 0 = * N E 0 W S d e t c e n n o c s i d 0 W S d e t c e n n o c 0 W S 1 = * N E 1 W S 0 = * N E 1 W S d e t c e n n o c s i d 1 W S d e t c e n n o c 1 W S 1 = * N E W S 0 = * N E 2 W S d e t c e n n o c s i d 2 W S d e t c e n n o c 2 W S h c t i w St u o Re m i T f f O / n O 0 W S0 5 Ω s n 0 0 1 1 W S0 5 Ω s n 0 0 1 2 W S0 5 Ω s n 0 0 1 |
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