Revision 2.05/Jan 2001 ã2001 Semtech Corp

www.semtech.com

8

ACS8515 LC/P

ADVANCED COMMUNCIATIONS

FINAL

locking. The cnfg_freq_divn register contains

the divider ratio N where the reference input

cnfg_ref_source_frequency register must be set

to the closest supported spot frequency to the

input frequency, but must be lower than the

input frequency. When using the “DivN” feature

the post-divider frequency must be 8 kHz, which

is indicated by setting the ‘lock8k’ bit high (bit

6 in cnfg_ref_source_frequency register). Any

input set to DivN must have the frequency

monitors disabled (if the frequency monitors

are disabled, they are disabled for all inputs

regardless of the input configurations, in this

case only activity monitoring will take place).

Whilst any number of inputs can be set to use

the “DivN” feature, only one N can be

programmed, hence all inputs using the “DivN”

feature must require the same division to get

to 8 kHz.

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2-

-

Table 1: Input Reference Source Selection and Group allocation

Notes for Table 1.

Note 1. TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency

being 77.76 MHz. The actual spot frequencies are 8 kHz (N x 8 kHz), 1.544/2.048 MHz, 6.48 MHz, 19.44 MHz, 25.92 MHz,

38.88 MHz, 51.84 MHz and 77.76 MHz.

Note 2. PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz. There are different output

clock frequencies available for SONET and SDH applications. F

selection and F

Note 3. The default priority values in brackets are the default numbers reported in the register map, which match up with the

ACS8510.

On power up, or by reset, the default will be set by the SONSDHB pin. Specific frequencies and priorities are set by

configuration. For SONET, config_mode register 34 Hex, bit 2 = 1. For SDH config_mode register 34 Hex, bit 2 = 0.