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ACS8515LC Datasheet(PDF) 8 Page - Semtech Corporation |
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ACS8515LC Datasheet(HTML) 8 Page - Semtech Corporation |
8 / 47 page Revision 2.05/Jan 2001 ã2001 Semtech Corp www.semtech.com 8 ACS8515 LC/P ADVANCED COMMUNCIATIONS FINAL locking. The cnfg_freq_divn register contains the divider ratio N where the reference input will get divided by (N+1) where 0<N<214-1. The cnfg_ref_source_frequency register must be set to the closest supported spot frequency to the input frequency, but must be lower than the input frequency. When using the DivN feature the post-divider frequency must be 8 kHz, which is indicated by setting the lock8k bit high (bit 6 in cnfg_ref_source_frequency register). Any input set to DivN must have the frequency monitors disabled (if the frequency monitors are disabled, they are disabled for all inputs regardless of the input configurations, in this case only activity monitoring will take place). Whilst any number of inputs can be set to use the DivN feature, only one N can be programmed, hence all inputs using the DivN feature must require the same division to get to 8 kHz. e m a N t r o P t r o P t u p n I y g o l o n h c e T d e t r o p p u S s e i c n e u q e r Fp u o r G e c r u o S C E S tl u a f e D y ti r o ir P ) 3 e t o N ( 1 C E SS O M C / L T T z H M 0 0 1 o t p U) 1 e t o N ( z H k 8 :) T E N O S ( tl u a f e D 8 :) H D S ( tl u a f e Dk z H 11 ) 4 ( 2 C E SS O M C / L T T z H M 0 0 1 o t p U) 1 e t o N ( z H k 8 :) T E N O S ( tl u a f e D z H k 8 :) H D S ( tl u a f e D 2) 5 ( 3 1 C E S L C E P / S D V L S D V Ltl u a f e d z H M 2 5 . 5 5 1 o t p U) 2 e t o N ( z H M 4 4 . 9 1 :) T E N O S ( tl u a f e D z H M 4 4 . 9 1 :) H D S ( tl u a f e D 1) 6 ( 2 2 C E S S D V L / L C E P tl u a f e d L C E P z H M 2 5 . 5 5 1 o t p U) 2 e t o N ( z H M 4 4 . 9 1 :) T E N O S ( tl u a f e D z H M 4 4 . 9 1 :) H D S ( tl u a f e D 2) 7 ( 4 3 C E SS O M C / L T T z H M 0 0 1 o t p U) 1 e t o N ( z H M 4 4 . 9 1 :) T E N O S ( tl u a f e D z H M 4 4 . 9 1 :) H D S ( tl u a f e D 3) 0 1 ( 5 1 C N Y SS O M C / L T Tc n y S e m a r F it l u M z H k 2- - Table 1: Input Reference Source Selection and Group allocation Notes for Table 1. Note 1. TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being 77.76 MHz. The actual spot frequencies are 8 kHz (N x 8 kHz), 1.544/2.048 MHz, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz and 77.76 MHz. Note 2. PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz. There are different output clock frequencies available for SONET and SDH applications. F 1/F2 means that the output frequency is F1 for SONET mode selection and F 2 for SDH mode selection. Note 3. The default priority values in brackets are the default numbers reported in the register map, which match up with the ACS8510. On power up, or by reset, the default will be set by the SONSDHB pin. Specific frequencies and priorities are set by configuration. For SONET, config_mode register 34 Hex, bit 2 = 1. For SDH config_mode register 34 Hex, bit 2 = 0. |
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