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MAX3946ETG Datasheet(PDF) 5 Page - Maxim Integrated Products

Part # MAX3946ETG
Description  1Gbps to 11.3Gbps, SFP Laser Driver with Laser Impedance Mismatch Tolerance
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX3946ETG Datasheet(HTML) 5 Page - Maxim Integrated Products

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_______________________________________________________________________________________ 5
1Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.85V to +3.63V, TA = -40°C to +85°C, and Figure 1. Guaranteed by design and characterization from TA = -40°C to +95°C.
Typical values are at VCC = +3.3V, IBIAS = 60mA, IMOD = 40mA, 25I differential output load, and TA = +25°C, unless otherwise
noted.) (Note 2)
Note 2: Guaranteed by design and characterization (TA = -40NC to +95NC).
Note 3: BIAS is connected to 2.0V. TOUT+/TOUT- are connected through pullup inductors to a separate supply that is equal to VCCT.
Note 4: Stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and VCC =
VCCREF Q5%. VCCREF = 3.0V to 3.45V. Reference current measured at VCCREF, TA = +25NC.
Note 5: Measured with K28.5 data pattern at 10.7Gbps and with a (27 - 1 PRBS + 72 zeros + 27 - 1 PRBS (inverted) + 72 ones)
pattern at 11.3Gbps.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONTROL I/O SPECIFICATIONS
DISABLE Input Current
IIH
12
F
A
IIL
Depends on pullup resistance
500
800
DISABLE Input High Voltage
VIH
1.8
VCC
V
DISABLE Input Low Voltage
VIL
0
0.8
V
DISABLE Input Resistance
RPULL
Internal pullup resistor
4.7
7.5
10
kI
3-WIRE DIGITAL I/O SPECIFICATIONS (SDA, SCL, CSEL)
Input High Voltage
VIH
2.0
VCC
V
Input Low Voltage
VIL
0.8
V
Input Hysteresis
VHYST
80
mV
Input Leakage Current
IIL, IIH
VIN = 0V or VCC, internal pullup or
pulldown is 75kI typical
150
F
A
Output High Voltage
VOH
External pullup is (4.7kI to 10kI) to VCC
VCC - 0.5
V
Output Low Voltage
VOL
External pullup is (4.7kI to 10kI) to VCC
0.4
V
3-WIRE DIGITAL INTERFACE TIMING CHARACTERISTICS (Figure 5)
SCL Clock Frequency
fSCL
400
1000
kHz
SCL Pulse-Width High
tCH
0.5
F
s
SCL Pulse-Width Low
tCL
0.5
F
s
SDA Setup Time
tDS
100
ns
SDA Hold Time
tDH
100
ns
SCL Rise to SDA Propagation
Time
tD
5
ns
CSEL Pulse-Width Low
tCSW
500
ns
CSEL Leading Time Before the
First SCL Edge
tL
500
ns
CSEL Trailing Time After the Last
SCL Edge
tT
500
ns
SDA, SCL Load
CB
Total bus capacitance on one line with
4.7kI pullup to VCC
20
pF


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