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CYRF69103-40LFXC Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CYRF69103-40LFXC Datasheet(HTML) 5 Page - Cypress Semiconductor |
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5 / 68 page  CYRF69103 Document #: 001-07611 Rev *F Page 5 of 68 6.6 SDR Mode Table 6-2. SDR Mode Register Value Description TX_CFG_ADR 0X3E 64 chip PN code, SDR mode, PA = 6 RX_CFG_ADR 0X4B AGC is enabled. LNA and attenuator are disabled. Fast turnaround is disabled, the device uses high side receive injection and Hi-Lo is disabled. Overwrite to receive buffer is enabled and RX buffer is configured to receive eight bytes maximum. Enables RXOW to allow new packets to be loaded into the receive buffer. This also enables the VALID bit which is used by the first generation radio’s error correction firmware. XACT_CFG_ADR 0X05 AutoACK is disabled. Forcing end state is disabled. The device is configured to transition to Idle mode after Receive or Transmit. ACK timeout is set to 128 µs. FRAMING_CFG_ADR 0X00 All SOP and framing features are disabled. Disable LEN_EN=0 if EOP is needed. TX_OVERRIDE_ADR 0X04 Disable Transmit CRC-16. RX_OVERRIDE_ADR 0X14 The receiver rejects packets with a zero seed. The RX CRC-16 checker is disabled and the receiver accepts bad packets that do not match the seed in the CRC_seed registers. This helps in communication with the first generation radio that does not have CRC capabilities. ANALOG_CTRL_ADR 0X01 Set ALL SLOW. When set, the synthesizer settle time for all channels is the same as the slow channels in the first generation radio, for manual ACK consistency DATA64_THOLD_ADR 0X07 Sets the number of allowed corrupted bits to 7 which is close to the recom- mended 12% value. EOP_CTRL_ADR 0xA1 Sets the number of consecutive symbols for non-correlation to detect end of packet. PREAMBLE_ADR 0xAAAA09 AAAA are the two preamble bytes. Any other byte can also be written into the preamble register file. Recommended counts of the preamble bytes to be sent must be >8. [+] Feedback |
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