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CYP15G0101DXB Datasheet(PDF) 11 Page - Cypress Semiconductor

Part # CYP15G0101DXB
Description  Single-channel HOTLink II Transceiver Compliant to multiple standards
Download  44 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYP15G0101DXB Datasheet(HTML) 11 Page - Cypress Semiconductor

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CYP15G0101DXB
CYV15G0101DXB
Document Number: 38-02031 Rev. *M
Page 11 of 44
OELE
LVTTL input,
asynchronous,
internal pull-up
Serial driver output enable latch enable. Active HIGH. When OELE = HIGH, the signals on
the BOE[1:0] inputs directly control the OUTx
± differential drivers. When the BOE[x] input is
HIGH, the associated OUTx
± differential driver is enabled. When the BOE[x] input is LOW,
the associated OUTx
± differential driver is powered down. When OELE returns LOW, the last
values present on BOE[1:0] are captured in the internal output enable latch. The specific
mapping of BOE[1:0] signals to transmit output enables is listed in Table 14. If the device is
reset (TRSTZ is sampled LOW), the latch is reset to disable both outputs.
BISTLE
LVTTL input,
asynchronous,
internal pull-up
Transmit and receive BIST latch enable. Active HIGH. When BISTLE = HIGH, the signals
on the BOE[1:0] inputs directly control the transmit and receive BIST enables. When the
BOE[x] input is LOW, the associated transmit or receive channel is configured to generate or
compare the BIST sequence. When the BOE[x] input is HIGH, the associated transmit or
receive channel is configured for normal data transmission or reception. When BISTLE
returns LOW, the last values present on BOE[1:0] are captured in the internal BIST enable
latch. The specific mapping of BOE[1:0] signals to transmit and receive BIST enables is listed
in Table 14. When the latch is closed, if the device is reset (TRSTZ is sampled LOW), the latch
is reset to disable BIST on both the transmit and receive channels.
RXLE
LVTTL input,
asynchronous,
internal pull-up
Receive channel power-control latch enable. Active HIGH. When RXLE = HIGH, the
signal on the BOE[0] input directly controls the power enable for the receive PLL and analog
logic. When the BOE[0] input is HIGH, the receive channel PLL and analog logic are active.
When the BOE[0] input is LOW, the receive channel PLL and analog logic are placed in a
non-functional power saving mode. When RXLE returns LOW, the last value present on
BOE[0] is captured in the internal RX PLL enable latch. The specific mapping of BOE[1:0]
signals to the receive channel enable is listed in Table 14. When the latch is closed, if the
device is reset (TRSTZ is sampled LOW), the latch is reset to disable the receive channel.
BOE[1:0]
LVTTL input,
asynchronous,
internal pull-up
BIST, serial output, and receive channel enables. These inputs are passed to and through
the output enable latch when OELE = HIGH, and captured in this latch when OELE returns
LOW. These inputs are passed to and through the BIST enable latch when BISTLE = HIGH,
and captured in this latch when BISTLE returns LOW. These inputs are passed to and through
the receive channel enable latch when RXLE = HIGH, and captured in this latch when RXLE
returns LOW.
LFI
LVTTL output,
asynchronous
Link fault indication output. Active LOW. LFI is the logical OR of four internal conditions:
1. Received serial data frequency outside expected range
2. Analog amplitude below expected levels
3. Transition density lower than expected
4. Receive channel disabled.
JTAG Interface
TMS
LVTTL input,
internal pull-up
Test mode select. Used to control access to the JTAG test modes. If maintained high for >
5 TCLK cycles, the JTAG test controller is reset. The TAP controller is also reset automatically
upon application of power to the device.
TCLK
LVTTL input,
internal pull-down
JTAG test clock.
TDO
Three-state LVTTL
output
Test data out. JTAG data output buffer which is high Z while JTAG test mode is not selected.
TDI
LVTTL input,
internal pull-up
Test data in. JTAG data input port.
Power
VCC
+3.3 V power
GND
Signal and power ground for all internal circuits.
Pin Descriptions
CYP(V)15G0101DXB single-channel HOTLink II (continued)
Pin Name
I/O Characteristics Signal Description
[+] Feedback


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