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CY62157ELL-45ZSXI Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY62157ELL-45ZSXI Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 18 page  CY62157E MoBL® 8-Mbit (512 K × 16) Static RAM Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-05695 Rev. *H Revised May 30, 2011 8-Mbit (512 K × 16) Static RAM Features ■ Very high speed: 45 ns ❐ Industrial: –40 °C to +85 °C ❐ Automotive-E: –40 °C to +125 °C ■ Wide voltage range: 4.5 V–5.5 V ■ Ultra low standby power ❐ Typical standby current: 2 A ❐ Maximum standby current: 8 A (Industrial) ■ Ultra low active power ❐ Typical active current: 1.8 mA at f = 1 MHz ■ Ultra low standby power ■ Easy memory expansion with CE1, CE2 and OE features ■ Automatic power down when deselected ■ CMOS for optimum speed and power ■ Available in Pb-free 44-pin TSOP II and 48-ball VFBGA package Functional Description The CY62157E is a high performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Place the device into standby mode when deseleMoBL®cted (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input or output pins (I/O0 through I/O15) are placed in a high impedance state when: ■ Deselected (CE1HIGH or CE2 LOW) ■ Outputs are disabled (OE HIGH) ■ Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) ■ Write operation is active (CE1 LOW, CE2 HIGH and WE LOW) To write to the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). To read from the device, take Chip Enable (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See Truth Table on page 12 for a complete description of read and write modes. Logic Block Diagram 512K x 16 RAM Array I/O0–I/O7 A8 A7 A6 A5 A2 COLUMN DECODER DATA IN DRIVERS OE A4 A3 I/O8–I/O15 WE BLE BHE A0 A1 A9 A10 CE2 CE1 Power Down Circuit BHE BLE CE2 CE1 [+] Feedback |
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