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CY25568SXCT Datasheet(PDF) 3 Page - Cypress Semiconductor |
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CY25568SXCT Datasheet(HTML) 3 Page - Cypress Semiconductor |
3 / 14 page CY25568 Document Number: 38-07111 Rev. *D Page 3 of 14 Pinouts Figure 1. CY25568 - 16 Pin SOIC General Description The Cypress CY25568 is a spread spectrum clock generator (SSCG) IC used for the purpose of reducing electro magnetic interference (EMI) found in today's high-speed digital electronic systems. The CY25568 uses a Cypress proprietary phase-locked loop (PLL) and spread spectrum clock (SSC) technology to synthesize and modulate the frequency of the digital clock. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies is greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency requirements and improve time to market without degrading system performance. The CY25568 input frequency range is 4 to 32 MHz and accepts clock, crystal, and ceramic resonator inputs. The output clocks can be programmed to produce 1x, 2x, and 4x multiplication of the input frequency with spread spectrum. A separate non-modulated reference clock is also provided. The use of 2x or 4x frequency multiplication eliminates the need for higher order crystals and allows the user to generate up to 128 MHz spread spectrum clock (SSC) by using only first order crystals. This reduces the cost while improving the system clock accuracy, performance and complexity center spread or down spread frequency modulation can be selected by the user based on 4 discrete values of Spread% for each spread mode with the option of a non-spread mode for system test and verification purposes. The CY25568 is available in a 16 pin SOIC (150-mil.) package with a commercial operating temperature range of 0 to 70 C. Contact Cypress for availability of –25 to +85 C industrial temperature range operation. Refer to CY25811/12/14 products for 8-pin SOIC package versions of the CY25568. Pin Definitions Pin Function Description 1 Xin/CLK Clock, crystal or ceramic resonator input pin 2VSS Power supply ground. 3VSS Power supply ground. 4 S1 Digital Spread% control pin 3-Level input (H-M-L). Default= M. 5 S0 Digital Spread% control pin 3-Level input (H-M-L). Default= M. 6 SSCLK1 Output clock. Refer to Table 2 on page 5 for frequency programmability. 7 REFOUT Reference clock output. The same frequency as Xin/CLK input. 8 SSCLK3 Output clock. Refer to Table 2 on page 5 for frequency programmability. 9 SSCLK2 Output clock. Refer to Table 2 on page 5 for frequency programmability. 10 PD# Power-down control Internally pulled to VDD, Default= High. 11 FRSEL Input frequency range selection digital control input 3-Level input (H-M-L). Default= M. 12 VDD Positive power supply. 13 VDD Positive power supply. 14 D0 3-Level (H-M-L) Digital output clock scaling control. Refer to Table 2 on page 5. Default= M. 15 D1 3-Level (H-M-L) Digital output clock scaling control. Refer to Table 2 on page 5. Default= M. 16 XOUT Crystal or ceramic resonator output pin 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XOUT D1 D0 VDD VDD FRSEL PD# SSCLK2 XIN/CLKIN VSS VSS S1 S0 SSCLK1 REFOUT SSCK3 CY25568 |
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