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CY25483SXI Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY25483SXI Datasheet(HTML) 1 Page - Cypress Semiconductor |
1 / 14 page CY25403/CY25423/CY25483 Three PLL Programmable Clock Generator with Spread Spectrum Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-12564 Rev. *F Revised July 18, 2011 Features ■ Three fully integrated phase-locked loops (PLLs) ■ Input frequency range ❐ External crystal: 8 to 48 MHz ❐ External reference: 8 to 166 MHz clock ■ Reference clock input voltage range ❐ 1.8 V for CY25403/CY25423/CY25483 ■ Wide operating output frequency range ❐ 3 to 166 MHz ■ Programmable spread spectrum with center and down spread option and lexmark and linear modulation profiles ■ VDD supply voltage options: ❐ 2.5 V, 3.0 V, and 3.3 V for CY25403/CY25423/CY25483 ■ Selectable output clock voltages independent of VDD supply: ❐ 2.5 V, 3.0 V, and 3.3 V for CY25403/CY25423/CY25483 ■ Frequency select feature with option to select four different frequencies ■ Power-down, output enable, and SS ON/OFF controls ■ Low jitter, high accuracy outputs ■ Ability to synthesize nonstandard frequencies with Fractional-N capability ■ Three clock outputs with programmable drive strength ■ Glitch-free outputs while frequency switching ■ 8-pin SOIC package ■ Commercial and Industrial temperature ranges Benefits ■ Multiple high performance PLLs allow synthesis of unrelated frequencies ■ Nonvolatile programming for personalization of PLL frequencies, spread spectrum characteristics, drive strength, crystal load capacitance, and output frequencies ■ Application specific programmable EMI reduction using Spread Spectrum for clocks ■ Programmable PLLs for system frequency margin tests ■ Meets critical timing requirements in complex system designs ■ Suitability for PC, consumer, portable, and networking applications ■ Capable of Zero PPM frequency synthesis error ■ Uninterrupted system operation during clock frequency switch ■ Application compatibility in standard and low power systems Block Diagram OSC PLL1 PLL3 (SS) CLK3 (SS) CLK2 (No SS) CLK1 (SS) Crossbar Switch FS1 SSON XOUT XIN/ EXCLKIN PD#/OE PLL 2 (SS) FS0 MUX and Control Logic Output Dividers and Drive Strength Control |
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