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CY25483SXC Datasheet(PDF) 7 Page - Cypress Semiconductor |
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CY25483SXC Datasheet(HTML) 7 Page - Cypress Semiconductor |
7 / 14 page CY25403/CY25423/CY25483 Document #: 001-12564 Rev. *F Page 7 of 14 AC Electrical Specifications Parameter Description Conditions Min Typ Max Unit FIN (crystal) Crystal frequency, XIN – 8 – 48 MH z FIN (clock) Input clock frequency (EXCLKIN) – 8 – 166 MH z FCLK Output clock frequency – 3 – 166 MH z DC Output duty cycle, all clocks except ref out Duty Cycle is defined in Figure 3 on page 8; t1/t2, measured at 50% of VDD 45 50 55 % DC Ref out duty cycle Ref In Min 45%, Max 55% 40 – 60 % TRF1 [3] Output rise/fall time Measured from 20% to 80% of VDD, as shown in Figure 4 on page 8, CL = 15 pF, drive strength [00] –6.8 – ns TRF2 [3] Output rise/fall time Measured from 20% to 80% of VDD, as shown in Figure 4 on page 8, CL = 15 pF, drive strength [01] –3.4 – ns TRF3 [3] Output rise/fall time Measured from 20% to 80% of VDD, as shown in Figure 4 on page 8, CL = 15 pF, drive strength [10] –2.0 – ns TRF4 [3] Output rise/fall time Measured from 20% to 80% of VDD, as shown in Figure 4 on page 8, CL = 15 pF, drive strength [11] –1.0 – ns TCCJ [3, 4] Cycle-to-cycle jitter (peak) Configuration dependent. See Table Configuration Example for C-C Jitter – 100 – ps TLOCK [3] PLL lock time Measured from 90% of the applied power supply level –1 3 ms Configuration Example for C-C Jitter Ref. Frequency (MHz) CLK1 Output CLK2 Output CLK3 Output Freq. (MHz) C-C Jitter Typ (ps) Freq. (MHz) C-C Jitter Typ (ps) Freq. (MHz) C-C Jitter Typ (ps) 14.3181 8.0 134 166 103 48 92 19.2 74.25 99 166 94 8 91 27 48 67 27 109 166 103 48 48 93 27 123 166 137 Recommended Crystal Specification for SMD Package Parameter Description Range 1 Range 2 Range 3 Unit Fmin Minimum frequency 8 14 28 MHz Fmax Maximum frequency 14 28 48 MHz R1 Motional resistance (ESR) 135 50 30 C0 Shunt capacitance 4 4 2 pF CL Parallel load capacitance 18 14 12 pF DL(max) Maximum crystal drive level 300 300 300 µW |
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