CY22150

Document #: 38-07104 Rev. *K

Page 7 of 18

Stable operation of the CY22150 cannot be guaranteed if the

100 MHz.

PLL Post Divider Options [0CH(7..0)], [47H(7..0)]

The output of the VCO is routed through two independent

muxes, then to two divider banks to determine the final clock

output frequency. The mux determines if the clock signal feeding

into the divider banks is the calculated VCO frequency or REF.

There are two select muxes (DIV1SRC and DIV2SRC) and two

divider banks (Divider Bank 1 and Divider Bank 2) used to

determine this clock signal. The clock signal passing through

DIV1SRC and DIV2SRC is referred to as DIV1CLK and

DIV2CLK, respectively.

The divider banks have four unique divider options available: /2,

/3, /4, and /DIVxN. DIVxN is a variable that can be independently

programmed (DIV1N and DIV2N) for each of the two divider

banks. The minimum value of DIVxN is 4. The maximum value

of DIVxN is 127. A value of DIVxN below 4 is not guaranteed to

work properly.

DIV1SRC is a single bit variable, controlled by register 0CH. The

remaining seven bits of register 0CH determine the value of post

divider DIV1N.

DIV2SRC is a single bit variable, controlled by register 47H. The

remaining seven bits of register 47H determine the value of post

divider DIV2N.

Register 0CH and 47H are defined in Table 8.

Charge Pump Settings [40H(2..0)]

The correct pump setting is important for PLL stability. Charge

pump settings are controlled by bits (4..2) of register 40H, and

are dependent on internal variable PB (see “PLL Frequency, P

Counter[40H(1..0)], [41H(7..0)], [42H(7)]”). Table 9 on page 7

summarizes the proper charge pump settings, based on Ptotal.

See Table 10 on page 7 for register 40H bit locations and values.

Although using the above table guarantees stability, it is recommended to use the Print Preview function in CyClocksRT to determine

the correct charge pump settings for optimal jitter performance.

PLL stability cannot be guaranteed for values below 16 and above 1023. If values above 1023 are needed, use CyClocksRT to

determine the best charge pump setting.

Table 6. Input Load Capacitor Register Bit Settings

Address

D7

D6

D5

D4

D3

D2

D1

D0

13H

CapLoad(7)

CapLoad(6)

CapLoad(5)

CapLoad(4)

CapLoad(3)

CapLoad(2)

CapLoad(1)

CapLoad(0)

Table 7. P Counter and Q Counter Register Definition

Address

D7

D6

D5

D4

D3

D2

D1

D0

40H

1

1

0

Pump(2)

Pump(1)

Pump(0)

PB(9)

PB(8)

41H

PB(7)

PB(6)

PB(5)

PB(4)

PB(3)

PB(2)

PB(1)

PB(0)

42H

PO

Q(6)

Q(5)

Q(4)

Q(3)

Q(2)

Q(1)

Q(0)

Table 8. PLL Post Divider Options

Address

D7

D6

D5

D4

D3

D2

D1

D0

0CH

DIV1SRC

DIV1N(6)

DIV1N(5)

DIV1N(4)

DIV1N(3)

DIV1N(2)

DIV1N(1)

DIV1N(0)

47H

DIV2SRC

DIV2N(6)

DIV2N(5)

DIV2N(4)

DIV2N(3)

DIV2N(2)

DIV2N(1)

DIV2N(0)

Table 9. Charge Pump Settings

Charge Pump Setting – Pump(2..0)

000

16 – 44

001

45 – 479

010

480 – 639

011

640 – 799

100

800 – 1023

101, 110, 111

Do not use – device will be unstable

Table 10. Register 40H Change Pump Bit Settings

Address

D7

D6

D5

D4

D3

D2

D1

D0

40H

1

1

0

Pump(2)

Pump(1)

Pump(0)

PB(9)

PB(8)

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