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CY14E064I Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY14E064I
Description  64-Kbit (8 K x 8) Serial (I2C) nvSRAM with Real Time Clock
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY14E064I Datasheet(HTML) 7 Page - Cypress Semiconductor

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PRELIMINARY
CY14C064I
CY14B064I, CY14E064I
Document #: 001-68169 Rev. **
Page 7 of 41
Slave Device Address
Every slave device on an I2C bus has a device select address.
The first byte after START condition contains the slave device
address with which the master intends to communicate. The
seven MSBs are the device address and the LSB (R/W bit) is
used for indicating Read or Write operation. The CY14X064I
reserves three sets of upper 4 MSBs [7:4] in the slave device
address field for accessing the Memory, RTC Registers, and
Control Registers. The accessing mechanism is described in the
following section.
The nvSRAM product provides three different functionalities:
Memory, RTC Registers and Control Registers functions (such
as serial number and product ID). The three functions of the
device are accessed through different slave device addresses.
The first four most significant bits [7:4] in the device address
register are used to select between the nvSRAM functions.
Memory Slave Device
The nvSRAM device is selected for read/write if the master
issues the slave address as 1010b followed by three bits of
device select. If the slave address sent by the master matches
with the Memory Slave device address then depending on the
R/W bit of the slave address, the data will be either read from
(R/W = ‘1’) or written to (R/W = ‘0’) the nvSRAM.
The address length for CY14X064I is 13 bits and thus it requires
2 address bytes to map the entire memory address location. The
dedicated two address bytes represent bit A0 to A12. However,
since the address is only 13-bits, it implies that the first three
MSB bits that is fed in is ignored by the device. Although these
bits are ‘don’t care’, Cypress recommends that this bit is treated
as 0 to enable seamless transition to higher memory densities.
RTC Registers Slave Device
The RTC Registers is selected for read/write if the master issues
the slave address as 1101b followed by three bits of device
select. Then, depending on the R/W bit of the slave address,
data is either read from (R/W = ‘1’) or written to (R/W = ‘0’) the
RTC Registers. The RTC Registers slave address is followed by
one byte address of RTC Register for read/write operation. The
RTC Registers map is explained in the Table 10.
Control Registers Slave Device
The Control Registers Slave device includes the serial number,
product ID, Memory Control, and Command Register.
The nvSRAM Control Register Slave device is selected for
read/write if the master issues the slave address as 0011b
followed by three bits of device select. Then, depending on the
R/W bit of the slave address, data is either read from (R/W = ‘1’)
or written to (R/W = ‘0’) the device.
Table 1. Slave Device Addressing
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
nvSRAM
Function Select
CY14X064I Slave Devices
1
0
1
0
Device select ID
R/W Selects Memory
Memory, 8 K × 8
1
1
0
1
Device select ID
R/W
Selects RTC
Registers
RTC Registers, 16 × 8
0
0
1
1
Device select ID
R/W Selects Control
Registers
Control Registers
- Memory Control Register, 1 × 8
- Serial Number, 8 × 8
- Device ID, 4 × 8
- Command Register, 1 × 8
Figure 7. Memory Slave Device Address
handbook, halfpage
R/W
LSB
MSB
Slave ID
10
1
0
A2
A0
A1
Device Select
Figure 8. RTC Registers Slave Device Address
handbook, halfpage
R/W
LSB
MSB
Slave ID
11
0
1
A2
A0
A1
Device Select
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