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PRELIMINARY PSoC® 5: CY8C53 Family Datasheet Document Number: 001-66237 Rev. *A Page 89 of 106 11.6.5 USB 11.6.6 Universal Digital Blocks (UDBs) PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. See the component data sheets in PSoC Creator for full AC/DC specifications, APIs, and example code. Note 32. Rise/fall time matching (TR) not guaranteed, see USB Driver AC Specifications on page 70. Table 11-49. USB DC Specifications Parameter Description Conditions Min Typ Max Units VUSB_5 Device supply for USB operation USB configured, USB regulator enabled 4.35 – 5.25 V VUSB_3.3 USB configured, USB regulator bypassed 3.15 – 3.6 V VUSB_3 USB configured, USB regulator bypassed[32] 2.85 – 3.6 V IUSB_Configured Device supply current in device active mode, bus clock and IMO = 24 MHz VDDD = 5 V, FCPU = 1.5 MHz – 10 – mA VDDD = 3.3 V, FCPU = 1.5 MHz – 8 – mA IUSB_Suspended Device supply current in device sleep mode VDDD = 5 V, connected to USB host, PICU configured to wake on USB resume signal –0.5 – mA VDDD = 5 V, disconnected from USB host –0.3 – mA VDDD = 3.3 V, connected to USB host, PICU configured to wake on USB resume signal –0.5 – mA VDDD = 3.3 V, disconnected from USB host –0.3 – mA Table 11-50. UDB AC Specifications Parameter Description Conditions Min Typ Max Units Datapath Performance FMAX_TIMER Maximum frequency of 16-bit timer in a UDB pair – – 67.01 MHz FMAX_ADDER Maximum frequency of 16-bit adder in a UDB pair – – 67.01 MHz FMAX_CRC Maximum frequency of 16-bit CRC/PRS in a UDB pair – – 67.01 MHz PLD Performance FMAX_PLD Maximum frequency of a two-pass PLD function in a UDB pair – – 67.01 MHz Clock to Output Performance tCLK_OUT Propagation delay for clock in to data out, see Figure 11-51. 25 °C – 20 25 ns tCLK_OUT Propagation delay for clock in to data out, see Figure 11-51. Worst-case placement, routing, and pin selection – – 55 ns |
