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PSoC® 3: CY8C32 Family Data Sheet Document Number: 001-56955 Rev. *K Page 23 of 120 5.5 Nonvolatile Latches (NVLs) PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown in Table 5-2. The details for individual fields and their factory default settings are shown in Table 5-3:. Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase / write cycles is limited Table 5-2. Device Configuration NVL Register Map Register Address 7 6 5 4 3 2 1 0 0x00 PRT3RDM[1:0] PRT2RDM[1:0] PRT1RDM[1:0] PRT0RDM[1:0] 0x01 PRT12RDM[1:0] PRT6RDM[1:0] PRT5RDM[1:0] PRT4RDM[1:0] 0x02 XRESMEN PRT15RDM[1:0] 0x03 DIG_PHS_DLY[3:0] ECCEN DPS[1:0] Table 5-3. Fields and Factory Default Settings Field Description Settings PRTxRDM[1:0] Controls reset drive mode of the corresponding IO port. See “Reset Configuration” on page 40. All pins of the port are set to the same mode. 00b (default) - high impedance analog 01b - high impedance digital 10b - resistive pull up 11b - resistive pull down XRESMEN Controls whether pin P1[2] is used as a GPIO or as an external reset. See “Pin Descriptions” on page 10, XRES description. 0 (default for 68-pin and 100-pin parts) - GPIO 1 (default for 48-pin parts) - external reset DPS{1:0] Controls the usage of various P1 pins as a debug port. 00b - 5-wire JTAG 01b (default) - 4-wire JTAG 10b - SWD 11b - debug ports disabled ECCEN Controls whether ECC flash is used for ECC or for general configuration and data storage. See “Flash Program 0 (default) - ECC disabled 1 - ECC enabled DIG_PHS_DLY[3:0] Selects the digital clock phase delay. See the TRM for details. |
