CY7C4205/CY7C4215

CY7C4225/CY7C4245

Document Number: 001-45652 Rev. *B

Page 6 of 25

Architecture

The CY7C42X5 consists of an array of 256 to 1 K words & 4 K

words of 18 bits each (implemented by a dual-port array of

SRAM cells), a read pointer, a write pointer, control signals

(RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, HF, PAF,

FF). The CY7C42X5 also includes the control signals WXI, RXI,

WXO, RXO for depth expansion.

Resetting the FIFO

Upon power-up, the FIFO must be reset with a Reset (RS) cycle.

This causes the FIFO to enter the Empty condition signified by

EF being LOW. All data outputs go LOW after the falling edge of

RS only if OE is asserted. In order for the FIFO to reset to its

default state, a falling edge must occur on RS and the user must

not read or write while RS is LOW.

FIFO Operation

pins is written into the FIFO on each rising edge of the WCLK

signal. Similarly, when the REN signal is active LOW, data in the

will be presented on each rising edge of RCLK while REN is

WCLK for it to be a valid write function.

outputs when OE is deasserted. When OE is enabled (LOW),

output data on the FIFO that is read enabled.

The FIFO contains overflow circuitry to disallow additional writes

when the FIFO is full, and underflow circuitry to disallow

additional reads when the FIFO is empty. An empty FIFO

after additional reads occur.

Programming

The CY7C42X5 devices contain two 12-bit offset registers. Data

distance from Empty (Full) that the Almost Empty (Almost Full)

flags become active. If the user elects not to program the FIFO’s

flags, the default offset values are used (see Table 2). When the

Load LD pin is set LOW and WEN is set LOW, data on the inputs

LOW-to-HIGH transition of the write clock (WCLK). When the LD

pin and WEN are held LOW then data is written into the Full offset

register on the second LOW-to-HIGH transition of the Write

Clock (WCLK). The third transition of the Write Clock (WCLK)

again writes to the Empty offset register (see Table 1). Writing all

offset registers does not have to occur at one time. One or two

offset registers can be written and then, by bringing the LD pin

HIGH, the FIFO is returned to normal read/write operation. When

the LD pin is set LOW, and WEN is LOW, the next offset register

in sequence is written.

The contents of the offset registers can be read on the output

lines when the LD pin is set LOW and REN is set LOW; then,

data can be read on the LOW-to-HIGH transition of the Read

Clock (RCLK).

Note

1. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.

RXO

Read expansion

output

O Cascaded – Connected to RXI of next device.

RS

Reset

I

Resets device to empty condition. A reset is required before an initial read or write

operation after power-up.

OE

Output enable

I

When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected.

If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.

almost empty/

almost full flags

I

nized to RCLK, Almost Full synchronized to WCLK.)

Signal Name

Description

IO

Function

Table 1. Write Offset Register

LD

WEN

WCLK[1]

Selection

0

0

Writing to offset registers:

Empty Offset

Full Offset

0

1

No operation

1

0

Write into FIFO

1

1

No operation

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