CY7C1461AV33

CY7C1463AV33, CY7C1465AV33

36-Mbit (1 M × 36/2 M × 18/512 K × 72)

Flow-Through SRAM with NoBL™ Architecture

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

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408-943-2600

Document #: 38-05356 Rev. *I

Revised March 29, 2011

36-Mbit (1 M × 36/2 M × 18/512 K × 72) Flow-Through SRAM with NoBL™ Architecture

Features

cycles between write and read cycles

to use OE

CY7C1463AV33

available

in

JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and

non Pb-free 165-ball FBGA package. CY7C1465AV33

available in Pb-free and non-Pb-free 209-ball FBGA package

deselect

Functional Description

3.3 V, 1 M × 36/2 M × 18/512 K × 72 Synchronous Flow-Through

Burst SRAMs designed specifically to support unlimited true

back-to-back read and write operations without the insertion of

wait states. The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is

equipped with the advanced NoBL logic required to enable

consecutive read and write operations with data being

transferred on every clock cycle. This feature dramatically

improves the throughput of data through the SRAM, especially

in systems that require frequent write-read transitions.

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock input is qualified by the

Clock Enable (CEN) signal, which when deasserted suspends

operation and extends the previous clock cycle. Maximum

access delay from the clock rise is 6.5 ns (133 MHz device).

Write operations are controlled by the two or four Byte Write

conducted with on-chip synchronous self timed write circuitry.

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence.

Selection Guide

133 MHz

100 MHz

Unit

Maximum Access Time

6.5

8.5

ns

Maximum Operating Current

310

290

mA

Maximum CMOS Standby Current

120

120

mA

Note

1. For best practices recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.

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