CY7C1460AV33-167AXC datasheet(1/28 Pages) CYPRESS

Part #	CY7C1460AV33-167AXC

Description	36-Mbit (1 M x 36/2 M x 18) Pipelined SRAM with NoBL Architecture

Download	28 Pages

Scroll/Zoom	100%

Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

Logo

1 / 28 page

CY7C1460AV33

CY7C1462AV33

36-Mbit (1 M × 36/2 M × 18)

Pipelined SRAM with NoBL™ Architecture

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

, CA 95134-1709

•

408-943-2600

Document Number: 38-05353 Rev. *I

Revised March 28, 2011

36-Mbit (1 M × 36/2 M × 18/512 K × 72) Pipelined SRAM with NoBL™ Architecture

Features

■ Pin compatible and functionally equivalent to ZBT

■ Supports 250 MHz bus operations with zero wait states

❐ Available speed grades are 250, 200 and 167 MHz

■ Internally self timed output buffer control to eliminate the need

to use asynchronous OE

■ Fully registered (inputs and outputs) for pipelined operation

■ Byte write capability

■ 3.3 V power supply

■ 3.3 V/2.5 V I/O power supply

■ Fast clock-to-output times

❐ 2.6 ns (for 250 MHz device)

■ Clock enable (CEN) pin to suspend operation

■ Synchronous self timed writes

■ CY7C1460AV33, CY7C1462AV33 available in

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non

Pb-free 165-ball FBGA package.

■ IEEE 1149.1 JTAG-compatible boundary scan

■ Burst capability—linear or interleaved burst order

■ “ZZ” sleep mode option and stop clock option

Functional Description

The CY7C1460AV33/CY7C1462AV33 are 3.3 V, 1 M × 36/2 M × 18

synchronous pipelined burst SRAMs with No Bus Latency™

(NoBL

 logic, respectively. They are designed to support

unlimited true back-to-back read/write operations with no wait

states. The CY7C1460AV33/CY7C1462AV33 are equipped with

the advanced (NoBL) logic required to enable consecutive

read/write operations with data being transferred on every clock

cycle. This feature dramatically improves the throughput of data

in systems that require frequent write/read transitions. The

CY7C1460AV33/CY7C1462AV33 are pin compatible and

functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. The clock

input is qualified by the clock enable (CEN) signal, which when

deasserted suspends operation and extends the previous clock

cycle.

Write operations are controlled by the byte write selects

(BWa–BWd

for

CY7C1460AV33

and

BWa–BWb

for

CY7C1462AV33) and a write enable (WE) input. All writes are

conducted with on-chip synchronous self timed write circuitry.

Three synchronous chip enables (CE1, CE2, CE3) and an

asynchronous output enable (OE) provide for easy bank

selection and output tristate control. To avoid bus contention, the

output drivers are synchronously tristated during the data portion

of a write sequence.

A0, A1, A

C

MODE

BW a

BW b

WE

CE1

CE2

CE3

OE

READ LOGIC

DQ s

DQ Pa

DQ Pb

DQ Pc

DQ Pd

D

A

T

A

S

T

E

R

I

N

G

O

U

T

P

U

T

B

U

F

E

R

S

MEMORY

ARRAY

E

INPUT

REGISTER 0

ADDRESS

REGISTER 0

WRITE ADDRESS

REGISTER 1

WRITE ADDRESS

REGISTER 2

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC

A0'

A1'

D1

D0

Q1

Q0

A0

A1

C

ADV/LD

E

INPUT

REGISTER 1

S

E

N

S

E

A

M

P

S

E

CLK

CEN

WRITE

DRIVERS

BW c

BW d

ZZ

SLEEP

CONTROL

O

U

T

P

U

T

R

E

G

I

S

T

E

R

S

Logic Block Diagram – CY7C1460AV33 (1 M × 36)

[+] Feedback

Similar Part No. - CY7C1460AV33-167AXC

Manufacturer	Part #	Datasheet	Description
Cypress Semiconductor	CY7C1460AV33-167AXC	395Kb / 27P	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture
	CY7C1460AV33-167AXC	513Kb / 27P	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture
	CY7C1460AV33-167AXC	1,000Kb / 31P	36-Mbit (1 M 횞 36/2 M 횞 18) Pipelined SRAM with NoBL??Architecture

More results

Similar Description - CY7C1460AV33-167AXC

Manufacturer	Part #	Datasheet	Description
Cypress Semiconductor	CY7C1470BV25	935Kb / 29P	72-Mbit (2 M x 36/4 M x 18) Pipelined SRAM with NoBL??Architecture
	CY7C1370D	1Mb / 33P	18-Mbit (512 K x 36/1 M x 18) Pipelined SRAM with NoBL Architecture
	CY7C1470V25	878Kb / 31P	72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
	CY7C1470BV33	1Mb / 33P	72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
	CY7C1470V25	506Kb / 39P	72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture June 27, 2013
	CY7C1470V33	721Kb / 38P	72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL??Architecture
	CY7C1470BV25	981Kb / 29P	72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
	CY7C1460BV25	721Kb / 30P	36-Mbit (1 M 횞 36/2 M 횞 18) Pipelined SRAM with NoBL??Architecture
	CY7C1460AV33	1,000Kb / 31P	36-Mbit (1 M 횞 36/2 M 횞 18) Pipelined SRAM with NoBL??Architecture
	CY7C1470BV33	1Mb / 34P	72-Mbit (2 M x 36/4 M 횞 18/1 M x 72) Pipelined SRAM with NoBL??Architecture

More results

CY7C1460AV33-167AXC Datasheet(PDF) 1 Page - Cypress Semiconductor

CY7C1460AV33-167AXC Datasheet(HTML) 1 Page - Cypress Semiconductor

Similar Part No. - CY7C1460AV33-167AXC

Similar Description - CY7C1460AV33-167AXC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL