CY7C1081DV33

Document #: 001-53992 Rev. *C

Page 6 of 13

AC Switching Characteristics

Over the Operating Range [5]

Parameter

Description

–12

Unit

Min

Max

Read Cycle

100

–

s

Read cycle time

12

–

ns

Address to data valid

–

12

ns

Data hold from address change

3

–

ns

–

12

ns

OE LOW to data valid

–

7

ns

OE LOW to low-Z

1

–

ns

OE HIGH to high-Z [7]

–7

ns

3–

ns

–7

ns

0–

ns

–12

ns

Byte enable to data valid

–

7

ns

Byte enable to low-Z

1

–

ns

Byte disable to high-Z

–

7

ns

Write Cycle [9, 10]

Write cycle time

12

–

ns

9

–

ns

Address setup to write end

9

–

ns

Address hold from write end

0

–

ns

Address setup to write start

0

–

ns

WE pulse width

9

–

ns

Data setup to write end

7

–

ns

Data hold from write end

0

–

ns

WE HIGH to low-Z [7]

3–

ns

WE LOW to high-Z [7]

–7

ns

Byte enable to end of write

9

–

ns

Notes

5. Test conditions are based on signal transition time of 3 ns or less and timing reference levels of 1.5 V and input pulse levels of 0 to 3.0 V. Test conditions for the read

cycle use output loading shown in part a) of AC Test Loads and Waveforms[2], unless specified otherwise.

8. These parameters are guaranteed by design and are not tested.

initiate a write, and the transition of any of these signals can terminate the write. The input data setup and hold timing must be referenced to the leading edge of the

signal that terminates the write.

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