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CY7C1081DV33-12BAXI Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CY7C1081DV33-12BAXI Datasheet(HTML) 6 Page - Cypress Semiconductor |
6 / 13 page CY7C1081DV33 Document #: 001-53992 Rev. *C Page 6 of 13 AC Switching Characteristics Over the Operating Range [5] Parameter Description –12 Unit Min Max Read Cycle tpower VCC(typ) to the first access [6] 100 – s tRC Read cycle time 12 – ns tAA Address to data valid – 12 ns tOHA Data hold from address change 3 – ns tACE CE1 LOW and CE2 HIGH to Data Valid – 12 ns tDOE OE LOW to data valid – 7 ns tLZOE OE LOW to low-Z 1 – ns tHZOE OE HIGH to high-Z [7] –7 ns tLZCE CE1 LOW and CE2 HIGH to low-Z [7] 3– ns tHZCE CE1 HIGH and CE2 LOW to high-Z [7] –7 ns tPU CE1 LOW and CE2 HIGH to power-up [8] 0– ns tPD CE1 HIGH and CE2 LOW to power-down [8] –12 ns tDBE Byte enable to data valid – 7 ns tLZBE Byte enable to low-Z 1 – ns tHZBE Byte disable to high-Z – 7 ns Write Cycle [9, 10] tWC Write cycle time 12 – ns tSCE CE1 LOW and CE2 HIGH to write end 9 – ns tAW Address setup to write end 9 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 9 – ns tSD Data setup to write end 7 – ns tHD Data hold from write end 0 – ns tLZWE WE HIGH to low-Z [7] 3– ns tHZWE WE LOW to high-Z [7] –7 ns tBW Byte enable to end of write 9 – ns Notes 5. Test conditions are based on signal transition time of 3 ns or less and timing reference levels of 1.5 V and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use output loading shown in part a) of AC Test Loads and Waveforms[2], unless specified otherwise. 6. tpower is the minimum amount of time that the power supply must be at typical VCC values until the first memory access can be performed. 7. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms[2]. 8. These parameters are guaranteed by design and are not tested. 9. The internal memory write time is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. Chip enables must be active and WE and byte enables must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data setup and hold timing must be referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. [+] Feedback |
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