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CY7C1081DV33-12BAXI Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CY7C1081DV33-12BAXI Datasheet(HTML) 5 Page - Cypress Semiconductor |
5 / 13 page CY7C1081DV33 Document #: 001-53992 Rev. *C Page 5 of 13 Figure 2. AC Test Loads and Waveforms[2] Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ Max Unit VDR VCC for data retention 2 – – V ICCDR Data retention current VCC=2V,CE1 > VCC – 0.2 V, CE2 < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V –– 100 mA tCDR[3] Chip deselect to data retention time 0– – ns tR[4] Operation recovery time 12 – – ns Figure 3. Data Retention Waveform 90% 10% 3.0 V GND 90% 10% ALL INPUT PULSES 3.3 V OUTPUT 5 pF* INCLUDING JIG AND SCOPE (b) R1 317 R2 351 RISE TIME: FALL TIME: > 1 V/ns (c) OUTPUT 50 Z0 = 50 VTH = 1.5 V 30 pF* * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT HIGH-Z CHARACTERISTICS: (a) > 1 V/ns 3.0 V 3.0 V tCDR VDR > 2 V DATA RETENTION MODE tR CE1 VCC CE2 Notes 2. Valid SRAM operation does not occur until the power supplies reach the minimum operating VDD (3.0 V). 100 s (tpower) after reaching the minimum operating VDD, normal SRAM operation begins to include reduction in VDD to the data retention (VCCDR, 2.0 V) voltage. 3. Tested initially and after any design or process changes that may affect these parameters. 4. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s. [+] Feedback |
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