CY7C1021D_11 datasheet(7/16 Pages) CYPRESS

Part #	CY7C1021D

Description	1-Mbit (64 K 횞 16) Static RAM CMOS for Optimum Speed and Power

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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7 / 16 page

CY7C1021D

Document #: 38-05462 Rev. *J

Page 7 of 16

Data Retention Characteristics

Over the Operating Range

Parameter

Description

Conditions

Min

Max

Unit

VDR

VCC for Data Retention

2.0

–

V

ICCDR

Data Retention Current

VCC = VDR = 2.0 V, CE > VCC – 0.3 V,

VIN > VCC – 0.3 V or VIN < 0.3 V

–3

mA

tCDR [10]

Chip Deselect to Data Retention Time

0

–

ns

tR [11]

Operation Recovery Time

tRC

–ns

Data Retention Waveform

4.5 V

tCDR

VDR > 2 V

DATA RETENTION MODE

tR

CE

VCC

Switching Waveforms

Figure 3. Read Cycle No. 1 (Address Transition Controlled) [12, 13]

PREVIOUS DATA VALID

DATA VALID

RC

tAA

tOHA

tRC

ADDRESS

DATA OUT

Notes

10. VIL (min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns.

11. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.

12. Device is continuously selected. OE, CE, BHE and/or BLE = VIL.

13. WE is HIGH for read cycle.

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