CY7C1021CV26

Document Number: 38-05589 Rev. *F

Page 7 of 16

Write Cycle[10]

Write cycle time

15

–

ns

CE LOW to write end

10

–

ns

Address set-up to write end

10

–

ns

Address hold from write end

0

–

ns

Address set-up to write start

0

–

ns

WE pulse width

10

–

ns

Data set-up to write end

8

–

ns

Data hold from write end

0

–

ns

WE HIGH to low Z[11]

3

–

ns

WE LOW to high Z[11, 12]

–

7

ns

Byte enable to end of write

9

–

ns

Over the Operating Range

Description

-15

Unit

Min

Max

Notes

10. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write, and

the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.

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