CY7C1011CV33

Document Number: 38-05232 Rev. *L

Page 7 of 17

Switching Characteristics

Over the Operating Range

Parameter [5]

Description

-10

-12

Unit

Min

Max

Min

Max

Read Cycle

1

–

1

–

s

Read cycle time

10

–

12

–

ns

Address to data valid

–

10

–

12

ns

Data hold from address change

3

–

3

–

ns

CE LOW to data valid

–

10

–

12

ns

OE LOW to data valid

Industrial/Automotive-A

–

5

–

6

ns

Automotive-E

–

–

–

8

OE LOW to Low Z[7]

0

–0–

ns

OE HIGH to High Z[7, 8]

–

5–6

ns

CE LOW to Low Z[7]

3

–3–

ns

CE HIGH to High Z[7, 8]

–

5–6

ns

CE LOW to power up

0

–

0

–

ns

CE HIGH to power down

–

10

–

12

ns

Byte enable to data valid

Industrial/Automotive-A

–

5

–

6

ns

Automotive-E

–

–

–

8

Byte enable to Low Z

0

–

0

–

ns

Byte disable to High Z

–

5

–

6

ns

Write Cycle [9, 10]

Write cycle time

10

–

12

–

ns

CE LOW to write end

7

–

8

–

ns

Address setup to write end

7

–

8

–

ns

Address hold from write end

0

–

0

–

ns

Address setup to write start

0

–

0

–

ns

WE pulse width

7

–

8

–

ns

Data setup to write end

5

–

6

–

ns

Data hold from write end

0

–

0

–

ns

WE HIGH to Low Z[7]

3

–3–

ns

WE LOW to High Z[7, 8]

–

5–6

ns

Byte enable to end of write

7

–

8

–

ns

Notes

5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V.

9. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write.

The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write.

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