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CY7C057V-15BBXC Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CY7C057V-15BBXC Datasheet(HTML) 6 Page - Cypress Semiconductor |
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6 / 26 page  CY7C056V CY7C057V Document #: 38-06055 Rev. *E Page 6 of 26 Pin Definitions Left Port Right Port Description A0L–A13/14L A0R–A13/14R Address (A0–A13 for 16K; A0–A14 for 32K devices) SEML SEMR Semaphore Enable CE0L, CE1L CE0R, CE1R Chip Enable (CE is LOW when CE0 VIL and CE1 VIH) INTL INTR Interrupt flag BUSYL BUSYR Busy flag I/O0L–I/O35L I/O0R–I/O35R Data bus input/output OEL OER Output Enable R/WL R/WR Read/Write Enable B0–B3 Byte select inputs. Asserting these signals enables read and write operations to the corresponding bytes of the memory array. BM, SIZE See bus matching for details. WA, BA See bus matching for details. M/S Master or Slave select VSS Ground VDD Power [+] Feedback |
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