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CY7C057V-15AXC Datasheet(PDF) 3 Page - Cypress Semiconductor |
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CY7C057V-15AXC Datasheet(HTML) 3 Page - Cypress Semiconductor |
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3 / 26 page  CY7C056V CY7C057V Document #: 38-06055 Rev. *E Page 3 of 26 Functional Description The CY7C056V and CY7C057V are low-power CMOS 16K and 32K x 36 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 36-bit dual-port static RAMs or multiple devices can be combined in order to function as a 72-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 72-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: Chip Enable (CE)[3], Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt Flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic Power-down feature is controlled independently on each port by Chip Select (CE0 and CE1) pins. The CY7C056V and CY7C057V are available in 144-Pin Thin quad plastic flatpack (TQFP) and 172-Ball ball grid array (BGA) packages. Note 3. CE is LOW when CE0 VIL and CE1 VIH. [+] Feedback |
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