CY2XP22

Crystal to LVPECL Clock Generator

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

•

408-943-2600

Document #: 001-10229 Rev. *F

Revised April 11, 2011

Features

(1.875 MHz to 20 MHz): 0.4 ps (typical)

Offset

Noise Power

1 kHz

–117 dBc/Hz

10 kHz

–126 dBc/Hz

100 kHz

–131 dBc/Hz

1 MHz

–131 dBc/Hz

Functional Description

The CY2XP22 is a PLL (Phase Locked Loop) based high

performance clock generator that uses an external reference

crystal. It is specifically targeted at FibreChannel and Gigabit

Ethernet applications. It produces a selectable output frequency

that is 2.5 or 5 times the crystal frequency. With a 25 MHz crystal,

the user can select either a 62.5 MHz or 125 MHz output. It uses

Cypress’s low noise VCO technology to achieve less than 1 ps

typical RMS phase jitter. The CY2XP22 has a crystal oscillator

interface input and one LVPECL output pair.

Logic Block Diagram

OUTPUT

DIVIDER

F_SEL

CRYSTAL

OSCILLATOR

CLK#

LOW -N OISE

PLL

CLK

XOUT

XIN

External

Crystal

Pinouts

Figure 1. Pin Diagram – 8-Pin TSSOP

1

2

36

7

8

XOUT

XIN

F_SEL

VSS

VDD

CLK#

45

VDD

CLK

Table 1. Pin Definitions – 8-Pin TSSOP

Pin Number

Pin Name

I/O Type

Description

1, 8

VDD

Power

3.3 V or 2.5 V power supply

2

VSS

Power

Ground

3, 4

XOUT, XIN

XTAL output and input

Parallel resonant crystal interface

5

F_SEL

CMOS input

Frequency Select: see Frequency Table

6,7

CLK#, CLK

LVPECL output

Differential clock output

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