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CY2DL1504 Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CY2DL1504 Datasheet(HTML) 6 Page - Cypress Semiconductor |
6 / 14 page CY2DL1504 Document Number: 001-56312 Rev. *F Page 6 of 14 AC Electrical Specifications (VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial)) Parameter Description Condition Min Typ Max Unit FIN Input frequency DC – 1.5 GHz FOUT Output frequency FOUT = FIN DC – 1.5 GHz tPD [8] Propagation delay input pair to output pair Input rise/fall time < 1.5 ns (20% to 80%) –– 480 ps tODC [9] Output duty cycle Diff input at 50% duty cycle Frequency range up to 1 GHz 48–52 % tSK1 [10] Output-to-output skew Any output to any output, with same load conditions at DUT –– 30 ps tSK1 D [10] Device-to-device output skew Any output to any output between two or more devices. Devices must have the same input and have the same output load. –– 150 ps PNADD Additive RMS phase noise 156.25 MHz Input Rise/fall time < 150 ps (20% to 80%) VID > 400 mV Offset = 1 kHz – – –120 dBc/Hz Offset = 10 kHz – – –135 dBc/Hz Offset = 100 kHz – – –135 dBc/Hz Offset = 1 MHz – – –150 dBc/Hz Offset = 10 MHz – – –154 dBc/Hz Offset = 20 MHz – – –155 dBc/Hz tJIT [11] Additive RMS phase jitter (Random) 156.25 MHz, 12 kHz to 20 MHz offset; input rise/fall time < 150 ps (20% to 80%), VID > 400 mV –– 0.11 ps tR, tF [12] Output rise/fall time, single-ended 50% duty cycle at input, 20% to 80% of full swing (VOL to VOH) Input rise/fall time < 1.5 ns (20% to 80%) Measured at 1 GHz. –– 300 ps tSOD Time from clock edge to outputs disabled Synchronous clock enable (CLK_EN) switched low –– 700 ps tSOE Time from clock edge to outputs enabled Synchronous clock enable (CLK_EN) switched high –– 700 ps Notes 8. Refer to Figure 5 on page 7. 9. Refer to Figure 6 on page 7. 10. Refer to Figure 7 on page 8. 11. Refer to Figure 8 on page 8. 12. Refer to Figure 9 on page 8. [+] Feedback |
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