Microsemi

Integrated Products

11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570

Page 3

Copyright

© 2000

Rev. 1.1, 2006-02-27

LX1689

Third Generation CCFL Controller

TM

®

DIM_CLK

Digital Dimming Clock / Dimming Polarity. An input pin that may be selected to control burst frequency for

external Digital Dimming. This input can be any clock signal up to 200KHz. This pin is also used to control the

dimming polarity when operating in the analog or internal digital mode. If DIM_MODE is in the open condition

(Analog Dimming Mode) the DIM_CLK input should be connected to VDD_A for conventional dimming polarity

or set to Ground for reverse polarity. Conventional polarity means that lamp brightness increases with

increasing voltage on the BRITE_IN pin. Reverse polarity means that brightness decreases with increasing

voltage.

OC_SNS

Over Current Sense Input. A full wave AC voltage input centered on ground that is proportional to total high

voltage transformer secondary winding current. The OC_SNS input is full wave rectified, then applied to a digital

comparator with a 2V reference to cause peak voltages greater than 2V to digitally reset the PWM logic on a

pulse by pulse basis.

Frequency range of the input signal is 10kHz to 500KHz. Normal operating voltage levels should be under

max ±1.8VPK, and abnormal voltage can operate continuously as high as ± 10V peak under load fault

conditions. Transients under fault conditions can reach ± 25VPK.

DIM_MODE

Dimming Mode Input. This three state input pin places the IC in Analog Dimming Mode, internal Digital Dimming

Mode, or external Digital Dimming Mode. If the input is left open or forced to VDD_A / 2 Analog mode is

selected.

If connected to VDD_A, Digital Dimming with a external clock source applied to the DIM_CLK input is

selected to the burst timing generator. If connected to Ground, Digital Dimming with a internal clock is selected.

The internal clock is equivalent to the frequency at AOUT divided by two, both the internal or external clock

frequency can be divided down by setting the DIV_248 pin. (see DIV_248)

OV_SNS

Over Voltage Sense Input. A full wave AC voltage input centered around ground that is proportional to lamp

voltage. The OV_SNS input will be full wave rectified, then applied to a digital comparator with a 2V reference to

cause peak voltage greaten than 2V to digitally reset the PWM logic on a pulse by pulse basis.

Frequency range of the input signal is 10Khz to 500KHz. Normal operating voltage levels should be under

±1.8VPK, and abnormal voltage can operate continuously as high as ±10V peak under load fault conditions.

Transients under fault conditions can reach ± 25VPK.

The input has a 10K pull down resistor that serves as a DC restorer to the external capacitor that divides

down lamp voltage.

DIV_248

Divide Digital Dimming clock by 2, 4, or 8. This three state input pin causes the internal or external digital

dimming clock source to be divided by one of the three values, 2, 4, or 8. Its purpose is to allow a selection of

three possible burst rates for any given external or internal clock source. A high (VDD_A) selects divide by 2,

open selects divide by 4, and ground selects divided by 8. We advise keeping burst above 95Hz and below

about 400HZ. This will minimize visible flicker and possible audible noise from the power supply components.

I_SNS

Current Sense Input. A full wave AC voltage input centered around ground that is proportional to lamp current.

The I_SNS input is full wave rectified and amplified, then presented to the inverting input of the current error

amplifier through a 100K resistor.

Frequency range of the input signal is 10KHz to 500KHz. Normal operating voltage levels will be in the range

of ± 0.5 to 2.5VPK, and abnormal voltage can operate continuously as high as ± 10V peak under load fault

conditions. Transient under fault conditions can reach ± 25VPK. We strongly recommend a 10K resistor be

placed in series with the pin to limit current from voltage spikes that can occur by intermittent lamp connectors,

or arcing from a faulty high voltage transformer. This resistor will eliminate the possibility of IC damage under

these fault conditions.

The open lamp fault logic monitors the I_SNS pin voltage and number of lamp current cycles. If the number

of lamp current cycles with amplitude below fault threshold are less than 8 in a given fault checking period then

the strike latch will not be reset and a fault is declared, which shuts down the A/B outputs. In the strike mode, if

no lamp current is detected after 15 attempts a fault is likewise declared. ( See further LX1689 operation

section)