TPS65182, TPS65182B

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SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010

It is possible for the host to force the TPS65182/TPS65182B directly into SLEEP mode from ACTIVE mode by

de-asserting the WAKEUP pin in which case the device follows the pre-defined power-down sequence before

entering SLEEP mode.

DEPENDENCIES BETWEEN RAILS

Charge pumps, LDOs, and VCOM driver are dependent on the positive and inverting buck-boost converters and

several dependencies exist that affect the power-up sequencing. These dependencies are listed below.

1. Inverting buck-boost (DCDC2) must be in regulation before positive boost (DCDC1) can be enabled.

Internally, DCDC1 enable is gated by DCDC2 power good.

2. Positive boost (DCDC1) must be in regulation before LDO2 (VNEG) can be enabled. Internally LDO2 enable

is gated DCDC1 power-good.

3. Positive boost (DCDC1) must be in regulation before VCOM can be enabled; Internally VCOM enable is

gated by DCDC1 power good.

4. Positive boost (DCDC1) must be in regulation before negative charge pump (CP2) can be enabled. Internally

CP2 enable is gated by DCDC1 power good.

5. Positive boost (DCDC1) must be in regulation before positive charge pump (CP1) can be enabled. Internally

CP1 enable is gated by DCDC1 power good.

6. LDO2 must be in regulation before LDO1 can be enabled. Internally LDO1 enable is gated by LDO2 power

good.

7. The minimum delay time between any two PWRx pins must be > 62.5 µs in order to follow the power up

sequence defined by GPIO control. If any two PWRx pins are pulled up together (< 62.5 µs apart) rails will

be staggered in a manner that a subsequent rail’s enable is gated by PG of a preceding rail. In this case, the

default order of power-up is LDO2 (VNEG), CP2 (VEE), LDO1 (VPOS), and CP1(VDDH). If any two PWRx

pins are pulled low then all rails will go down at the same time.

Copyright © 2010, Texas Instruments Incorporated

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Product Folder Link(s): TPS65182 TPS65182B