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SN75DP130DSRGZT Datasheet(PDF) 5 Page - Texas Instruments |
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SN75DP130DSRGZT Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 31 page  SN75DP130 www.ti.com SLLSE57 – APRIL 2011 PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. MAIN LINK TERMINALS IN0p, IN0n 38, 39 Input DisplayPort Main Link Lane 0 Differential Input (100 Ω diff) IN1p, IN1n 41, 42 DisplayPort Main Link Lane 1 Differential Input IN2p, IN2n 44, 45 DisplayPort Main Link Lane 2 Differential Input IN3p, IN3n 47, 48 DisplayPort Main Link Lane 3 Differential Input OUT0p, OUT0n 23, 22 Output DisplayPort Main Link Lane 0 Differential Output (100 Ω diff) OUT1p, OUT1n 20, 19 DisplayPort Main Link Lane 1 Differential Output OUT2p, OUT2n 17, 16 DisplayPort Main Link Lane 2 Differential Output OUT3p, OUT3n 14, 13 DisplayPort Main Link Lane 3 Differential Output AUX CHANNEL AND DDC DATA TERMINALS AUX_SRCp, 30, 29 I/O Source Side Bidirectional DisplayPort Auxiliary Data Channel. If the AUX_SNK AUX_SRCn (100 Ω diff) channel is used for monitoring only, these signals are not used and may be left open. AUX_SNKp, AUX_SNKn 28, 27 I/O Sink Side Bidirectional DisplayPort Auxiliary Data Channel. (100 Ω diff) SCL_DDC, SDA_DDC 33, 34 I/O Bidirectional I2C Display Data Channel (DDC) for TMDS mode. These signals may be utilized together with AUX_SNK to form a FET switch to short-circuit the AC coupling capacitors during TMDS operation in a DP++ Dual-Mode configuration. These terminals include integrated 60 k Ω pull-up resistors HPD, CAD, and CONTROL TERMINALS HPD_SRC 9 O Hot Plug Detect Output to the DisplayPort Source. HPD_SNK 11 I DisplayPort Hot Plug Detect Input from Sink. This device input is 5V tolerant. Note: Pull this input high during compliance testing or use I2C control interface to go into compliance test mode and control HPD_SNK and HPD_SRC by software. CAD_SRC 8 O DP Cable Adapter Detect Output. This output typically drives the GPU CAD input. CAD_SNK 10 I DisplayPort Cable Adapter Detect Input. This input tolerates a 5V supply with a supply impedance higher than 90k Ω. A device internal zener diode limits the input voltage to 3.3V. An external 1M Ω resistor to GND is recommended. This terminal is used to select DP mode or TMDS mode in a DP++ Dual-Mode application. SCL_CTL, SDA_CTL 4, 5 I/O Bidirectional I2C interface to configure the SN75DP130. This interface is active independent of the EN input but inactive when RSTN is low. RSTN 35 I Active Low Device Reset. This input includes a 150k Ω resistor to the VDDD core supply. An external capacitor to GND is recommended on the RSTN input to provide a power-up delay. This signal is used to place the SN75DP130 into Shutdown mode for the lowest power consumption. When the RSTN input is asserted, all outputs (excluding HPD_SRC and CAD_SRC) are high-impedance, and inputs (excluding HPD_SNK and CAD_SNK) are ignored; all I2C and DPCD registers are reset to their default values. At power up, the RSTN input must not be de-asserted until the VCC and VDDD supplies have reached at least the minimum recommended supply voltage level. EN 26 I Device Enable. This input incorporates an internal pullup of 200k Ω. ADDR_EQ 3 3-level Input I2C Target Address Select and EQ Configuration Input. If the I2C bus is used, this input setting selects the I2C target address, as described in Table 7. This input also configures the input EQ to the device, as described in Table 5. SUPPLY AND GROUND TERMINALS VDDD SN75DP130DS Digital low voltage core and Main Link supply for SN75DP130DS device option. 6, 12, 15, 21, 25, 32, 37, Nominally 1.1V. 43 VCC SN75DP130SS 3.3V Supply 1, 6, 12, 25, 32, 36 SN75DP130DS 1, 36 Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): SN75DP130 |
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