1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

DGND

NC

DVDD

CLKIN

NC

DATA

NC

DGND

AVDD

VINP

VINN

AGND

NC

(1)

NC

NC

AGND

CLKIN

DATA

t

D

t

CLK

t

HIGH

t

LOW

AMC1204

www.ti.com

SBAS512A

– APRIL 2011 – REVISED APRIL 2011

PIN CONFIGURATION

DW PACKAGE

TSSOP-16

(TOP VIEW)

(1) NC = no internal connection.

PIN DESCRIPTIONS

PIN NAME

PIN#

FUNCTION

DESCRIPTION

AVDD

1

Power

High-side power supply

VINP

2

Analog input

Noninverting analog input

VINN

3

Analog input

Inverting analog input

AGND

Power

High-side ground

DGND

9, 16

Power

Controller-side ground

DATA

11

Digital output Modulator data output

CLKIN

13

Digital input

Modulator clock input

DVDD

14

Power

Controller-side power supply

NC

5, 6, 7, 10, 12, 15

—

No internal connection; can be tied to any potential or left unconnected

(1)

Both pins are connected internally via a low-impedance path; thus, only one of the pins must be tied to the ground plane.

TIMING INFORMATION

Figure 1. Modulator Output Timing

TIMING CHARACTERISTICS FOR Figure 1

Over recommended ranges of supply voltage and operating free-air temperature, unless otherwise noted.

PARAMETER

MIN

TYP

MAX

UNIT

CLKIN clock period

45.5

50

200

ns

CLKIN clock high time

20

25

120

ns

CLKIN clock low time

20

25

120

ns

Delayed falling edge of CLKIN to DATA valid

2

15

ns

Copyright

© 2011, Texas Instruments Incorporated

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