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AD8283WBCPZ Datasheet(PDF) 6 Page - Analog Devices

Part # AD8283WBCPZ
Description  Radar Receive Path AFE: 6-Channel LNA/PGA/AAF with ADC
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD8283WBCPZ Datasheet(HTML) 6 Page - Analog Devices

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AD8283
Rev. 0 | Page 6 of 28
SWITCHING SPECIFICATIONS
AVDD18x = 1.8 V, AVDD33x = 3.3 V, DVDD18x = 1.8 V, DVDD33x = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE = 80
MSPS, RS = 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C,
unless otherwise noted.
Table 3.
Parameter1
Temperature
Min
Typ
Max
Unit
CLOCK
Clock Rate
Full
10
80
MSPS
Clock Pulse Width High (tEH) at 80 MSPS
Full
6.25
ns
Clock Pulse Width Low (tEL) at 80 MSPS
Full
6.25
ns
Clock Pulse Width High (tEH) at 40 MSPS
Full
12.5
ns
Clock Pulse Width Low (tEL) at 40 MSPS
Full
12.5
ns
OUTPUT PARAMETERS
Propagation Delay (tPD) at 80 MSPS
Full
1.5
2.5
5.0
ns
Rise Time (tR)
Full
1.9
ns
Fall Time (tF)
Full
1.2
ns
Data Set-Up Time (tDS) at 80 MSPS
Full
9.0
10.0
11.0
ns
Data Hold Time (tDH) at 80 MSPS
Full
1.5
4.0
5.0
ns
Data Set-Up Time (tDS) at 40 MSPS
Full
21.5
22.5
23.5
ns
Data Hold Time (tDH) at 40 MSPS
Full
1.5
4.0
5.0
ns
Pipeline Latency
Full
7
Clock cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
N –1
INAx
N
N – 7
N – 6
N – 5
N – 4
N – 3
N – 2
N – 1
N
CLK–
CLK+
D[11:0]
tPD
tEH
tEL
tDS
tDH
Figure 2. Timing Definitions for Switching Specifications


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