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AD6641BCPZ-500 Datasheet(PDF) 8 Page - Analog Devices |
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AD6641BCPZ-500 Datasheet(HTML) 8 Page - Analog Devices |
8 / 28 page AD6641 Rev. 0 | Page 8 of 28 SPI TIMING REQUIREMENTS Table 5. Parameter Description Limit Unit tDS Setup time between the data and the rising edge of SCLK 2 ns min tDH Hold time between the data and the rising edge of SCLK 2 ns min tCLK Period of the SCLK 40 ns min tS Setup time between CSB and SCLK 2 ns min tH Hold time between CSB and SCLK 2 ns min tHIGH SCLK pulse width high 10 ns min tLOW SCLK pulse width low 10 ns min tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge 10 ns min tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 10 ns min Timing Diagrams N– 1 N N+2 N+ 3 N+4 N+5 N+1 CLK+ CLK– VIN± tA tCH tCL Figure 2. Input Interface Timing PD[11:0] OUTPUT DATA BUS tCPD tPCLK tPCLK_CH tSKEW CLK+ CLK– PCLK+ PCLK– Figure 3. Parallel CMOS Mode Output Interface Timing SP_SDFS SP_SCLK tDSDFS Figure 4. SP_SDFS Propagation Delay |
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